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US 6,320,412 B1Granted
Architecture and interconnect for programmable logic circuits
AssigneeBTR, Inc. c/o Corporate Trust Co.
InventorsBenjamin S. Ting, Peter M. Pani
Life of this patent
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Abstract
An improved programmable logic device and interconnect architecture is provided. In one embodiment an interconnect network provides programmable routing between calls. In one embodiment the interconnect network includes first routing lines of a first level of routing lines, second routing lines of a second level of routing lines and third routing lines of a third level of routing lines. The first and second routing lines are programmably and bidirectionally coupled to the third routing lines such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from the third routing lines to the first routing lines and second routing lines.
Claims38
A programmable logic device comprising:
- a plurality of cells;
- and
- an interconnect network coupled to the cells, comprising:
- first routing lines of a first level of routing lines, wherein the first level of routing lines spans n logical blocks,
- second routing lines of a second level of routing lines, wherein the second level of routing lines span m+n logical blocks where m is different from n, and
- third routing lines of a third level of routing lines, said first and second routing lines programmably and directly bidirectionally coupled to the third routing lines, such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from third routing lines to the first routing lines and the second routing lines.
3 more elements
A programmable logic device comprising:
- a plurality of cells;
- and
- an interconnect network coupled to the cells, comprising:
- first routing lines of a first level of routing lines, wherein the first level of routing lines spans n logical blocks,
- second routing lines of a second level of routing lines, wherein the second level of routing lines spans k+m+n logical blocks where k is different from m and n and m is different from n, and
- third routing lines of a third level of routing lines, said first and second routing lines programmably and directly bidirectionally coupled to the third routing lines, such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from third routing lines to the first routing lines and the second routing lines.
3 more elements
A programmable logic circuit comprising:
- a first plurality of configurable cells organized in two dimensions, said configurable cells grouped into substantially same size regions to form a level of hierarchy;
- a second plurality of configurable cells, located in proximity together to form a first region, comprising a subset of configurable cells of said first plurality of cells;
- a first set of routing lines, spanning a dimension of said first region and configured to couple to input ports and output ports of configurable cells of said second plurality of configurable cells through a first set of switches, wherein an output port of a configurable cell of said second plurality of configurable cells is coupled to at least one input port of other configurable cells of the second plurality of configurable cells;
- a third plurality of configurable cells comprising at least the configurable cells of said second plurality of configurable cells to form a second region larger than said first region;
- a second set of routing lines, spanning a dimension of said second region and configured to couple to input ports and output ports of the configurable cells of said third plurality of configurable cells through a second set of switches, wherein an output port of a configurable cell of said third plurality of configurable cells selectively coupled to drive a first routing line of said second set of routing lines through said second set of switches;
- a third set of switches, said first set of routing lines selectively coupled to said second set of routing lines through the third set of switches;
- a fourth plurality of configurable cells comprising at least the configurable cells of said third plurality of configurable cells to form a third region larger than said second region;
- and
- a second routing line of a third set of routing lines, spanning a dimension of said third region and configured to couple to drive at least a third routing line of said first set of routing lines and said first routing line through a fourth set of switches.
6 more elements
A programmable logic circuit comprising:
- a first routing line, a second routing line, a third routing line, a fourth routing line, and a fifth routing line wherein said first, second, fourth and fifth routing lines have different spans;
- said first routing line selectively coupling to the third routing line through a first switch;
- said second routing line selectively coupling to the third routing line through a second switch;
- said third routing line selectively coupling to the fourth routing line through a third switch;
- and
- said third routing line selectively coupling to the fifth routing line through a fourth switch.
3 more elements
A method for programming a programmable logic circuit comprising:
- organizing a first plurality of configurable cells in two dimensions;
- grouping the first plurality of configurable cells into substantially same size regions to form a level of hierarchy;
- locating a second plurality of configurable cells in proximity to form a first region, the first region comprising a subset of configurable cells of said first plurality of cells;
- selectively coupling input ports and output ports of configurable cells of the second plurality of configurable cells through a first set of routing lines spanning a dimension of said first region, wherein an output port of a configurable cell of said second plurality of configurable cells is coupled to at least one input port of other configurable cells of the second plurality of configurable cells;
- locating a third plurality of configurable cells comprising at least the configurable cells of said second plurality of configurable cells to form a second region larger than said first region;
- selectively coupling an output port of a configurable cells of the third plurality of configurable cells to drive a first routing line of a second set of routing lines, routing lines of the second set of routing lines spanning a dimension of the second;
- selectively coupling the first set of routing lines to said second set of routing lines;
- locating a fourth plurality of configurable cells comprising at least the configurable cells of said third plurality of configurable cells to form a third region larger than said second region;
- and
- selectively coupling a second routing line of a third set of routing lines, spanning a dimension of said third region, to drive at least a third routing line of said first set of routing lines and said first routing line.
7 more elements
A method for programming a programmable logic circuit comprising:
- providing a first routing line, a second routing line, a third routing line, a fourth routing line, and a fifth routing line wherein said first, second, fourth and fifth routing lines have different spans;
- selectively coupling the first routing line to the third routing line;
- selectively coupling said second routing line to the third routing line;
- selectively coupling the third routing line to the fourth routing line;
- and
- selectively coupling said third routing line to the fifth routing line.
3 more elements
Dependencies are inferred from the claim text.