Heterogeneous CPLD logic blocks
AssigneeCypress Semiconductor Corporation
InventorsVinod Malhotra, Christopher W. Jones
Life of this patent
Estimating the term…
Abstract
A programmable logic device comprising a first plurality of logic blocks each comprising a first number of I/O macrocells, a second plurality of logic blocks each comprising a second number of I/O macrocells and a configuration circuit configured to enable one or more of said first plurality of logic blocks and/or one or more of said second plurality of logic blocks.
Claims17
A programmable logic device comprising:
- a first plurality of logic blocks each comprising a first number of I/O macrocells;
- a second plurality of logic blocks each comprising a second number of I/O macrocells;
- and
- a configuration circuit configured to enable one or more of said first plurality of logic blocks and/or one or more of said second plurality of logic blocks, wherein said first number is equal to a positive integer and said second number is zero.
A method for configuring a programmable logic device having a first plurality of logic blocks comprising a first number of I/O macrocells and a second plurality of logic blocks comprising a second number of I/O macrocells, comprising the steps of:
- (A) enabling one or more of said first plurality of logic blocks;
- and
- (B) enabling one or more of said second plurality of logic blocks, wherein said first number is equal to a positive integer and said second number is zero.
A method of defining two densities of programmable logic devices that have the same total number of I/O macrocells comprising the following steps:
- (A) assigning a number N1 to be the number of macrocells in the larger density device;
- (B) assigning a number M1 to be the number of macrocells in the smaller density device;
- (C) declaring a number J to be the number of macrocells in a logic block;
- (D) declaring a number K to be the total number of I/O macrocells in each device;
- (E) declaring a number N2 to be the quotient of the number N1 divided by the number J;
- (F) declaring a number M2 to be the quotient of the number M1 divided by the number J;
- (G) declaring a number M3 to be the quotient of the number K divided by the number M2;
- (H) declaring a number M4 to be the difference between the number J and the number M3;
- (I) declaring a number N5 to be the difference between the number N2 and the number M2;
- (J) assigning a first density device to have a number of logic blocks equal to M2, each with a number of I/O macrocells equal to M3 and a number of buried macrocells equal to M4;
- and
- (K) assigning a second density device to have a number of logic blocks equal to N5, each with a number of buried macrocells equal to J, and a number of logic blocks equal to M2, each with a number of I/O macrocells equal to M3 and a number of buried macrocells equal to M4.
A programmable logic device comprising a plurality of logic blocks having the same number of macrocells, wherein at least two of said plurality of logic blocks have a different number of I/O macrocells, at least one of said plurality of logic blocks has an I/O macrocell and at least one of said plurality of logic blocks does not have an I/O macrocell.
Dependencies are inferred from the claim text.