CMOS majority circuit

A majority circuit comprising:

• a bias circuit having first and second MOS transistors of the first gate conduction type and first and second MOS transistors of the second gate conduction type connected in series, the source of the first MOS transistor of the first gate conduction type and the gate of the second MOS transistor of the second gate conduction type being connected to the supply voltage, the gate of the first MOS transistor of the first gate conduction type and the source of the second MOS transistor of the second gate conduction type being grounded, the gate and the drain of the second transistor of the first gate conduction type and the gate and the drain of the first MOS transistor of the second gate conduction type being connected to a predetermined bias voltage;
• a binary signal detecting section including a plurality of detection circuits connected in parallel, each having third and fourth MOS transistors of the first gate conduction type and third and fourth MOS transistors of the second gate conduction type connected in series, the source of the third MOS transistor of the first gate conduction type being connected to the supply voltage, the source of the fourth MOS transistor of the second gate conduction type being grounded, the input sections connected respectively to the gate of the third MOS transistor of the first gate conduction type and the gate of the fourth MOS transistor of the second gate conduction type being adapted to receive a plurality of binary input signals, the gate of the fourth MOS transistor of the first gate conduction type and the gate of the third MOS transistor of the second gate conduction type being connected to said bias voltage, the drain of the fourth MOS transistor of the first gate conduction type and the drain of the third MOS transistor of the second conduction type being connected to a node;
• and
• an inverter circuit having fifth and sixth MOS transistors of the first gate conduction type and fifth and sixth MOS transistors of the second gate conduction type connected in series, the source of the fifth MOS transistor of the first gate conduction type and the gate of the sixth MOS transistor of the second gate conduction type being connected to the supply voltage, the gate of the fifth MOS transistor of the first gate conduction type and the source of the sixth MOS transistor of the second gate conduction type being grounded, the gate of the sixth MOS transistor of the first gate conduction type and the gate of the fifth MOS transistor of the second gate conduction type being connected to said node, the drain of the sixth MOS transistor of the first gate conduction type and the drain of the fifth MOS transistor of the second gate conduction type being connected to an output section to output a binary signal as the outcome of the majority decision.