Method for preparing a semiconductor wafer to receive a protective tape
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSen-Fu Chen, Kuei-Jen Chang
Life of this patent
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSen-Fu Chen, Kuei-Jen Chang
Estimating the term…
A protective tape is applied to the device side of a wafer (to protect it during an operation to grind the back side of the wafer) after the surface has been prepared to present only sloping surfaces to the tape. This profile prevents the otherwise sharp edges of the holes for the bonding pads from cutting into the adhesive of the tape and causing adhesive particles to remain on the wafer surface after the tape has been removed. Particles of resist can interfere with attaching wires to the bonding pads. The tape receiving surface of the wafer is commonly formed by a passivation layer and by bonding pad sites that are exposed through holes in the passivation layer. These sloping profiles can be formed by giving a sloping profile to the holes in the photoresist before the holes are etched. Alternatively the holes can be etched suitably wider at the top than at the bottom.
A method for manufacturing a semiconductor wafer comprising,
A method for manufacturing a semiconductor wafer having a substrate, a wafer back surface and a wafer device surface, a conductor layer overlying the substrate, a passivation film directly overlying the conductor layer, the method comprising,
A wafer comprising a substrate, a conductor layer overlying the substrate and patterned to interconnect circuit nodes below the conductive layer, a passivation layer directly overlying the conductor layer and having holes that expose regions of the conductive layer where wires can be attached for connection to external circuit nodes, the holes having a sloping profile with the upper diameter greater than the lower diameter, the slope being sufficient to prevent the upper edges of the holes from cutting through the adhesive of a protective tape applied to the surface of the passivation layer to protect the wafer during an operation to grind the back side of the wafer.
Dependencies are inferred from the claim text.