High aspect ratio metallization structures for shallow junction devices, and methods of forming the same

A contact residing in a high aspect ratio contact opening, wherein said high aspect ratio contact opening comprises at least one substantially vertical side wall intersecting a bottom surface, the intersection of the at least one substantially vertical side wall and the bottom surface forming a corner recessed within an active-device region, and wherein said contact comprises a contact interface comprising a substantially ring-shaped structure of silicide material, said substantially ring-shaped structure of silicide material having an inclined, concave, and inwardly facing upper surface and being disposed in the corner recessed within said active-device region such that a center area of the bottom surface of the high aspect ratio contact opening remains free of silicide material, said contact formed by a method comprising:

• providing a silicon-containing semiconductor substrate having a dielectric layer thereover, wherein at least one high aspect ratio contact opening extends through said dielectric layer and into at least one active-device region in said silicon-containing semiconductor substrate, forming a recess within said at least one active-device region;
• depositing a first conductive material in said at least one high aspect ratio contact opening with an IMP process at a high pedestal bias power;
• annealing said silicon-containing semiconductor substrate to react said first conductive material with said at least one active-device region to form said silicide material;
• removing a non-reacted portion of said first conductive material;
• and
• depositing a second conductive material in said at least one high aspect ratio contact opening.

A DRAM chip, having at least one contact interface residing in a high aspect ratio contact opening, wherein said high aspect ratio contact opening comprises at least one substantially vertical side wall intersecting a bottom surface, the intersection of the at least one substantially vertical side wall and the bottom surface forming a corner recessed within an active-device region, and wherein said contact interface comprises a substantially ring-shaped structure of silicide material, said substantially ring-shaped structure of silicide material having an inclined, concave, and inwardly facing upper surface and being disposed in the corner recessed within said active-device region such that a center area of the bottom surface of the high aspect ratio contact opening remains free of silicide material, said DRAM chip formed by a method comprising:

• providing a silicon-containing semiconductor substrate having a dielectric layer thereover, wherein at least one high aspect ratio contact opening extends through said dielectric layer and into at least one active-device region in said silicon-containing semiconductor substrate, forming a recess within said at least one active-device region;
• depositing a first conductive material in contact with said at least one active-device region within said at least one high aspect ratio contact opening by an IMP process at a high pedestal bias power;
• annealing said silicon-containing semiconductor substrate to react said first conductive material to form said silicide material;
• removing a non-reacted portion of said first conductive material;
• and
• depositing a second conductive material in said at least one high aspect ratio contact opening.

A contact comprising:

• a high aspect ratio contact opening comprising at least one substantially vertical side wall intersecting a bottom surface, the intersection of the at least one substantially vertical side wall and the bottom surface forming a corner recessed within an active-device region;
• a contact interface comprising a substantially ring-shaped structure of a first conductive material, said substantially ring-shaped structure comprising a silicide material, having an inclined, concave, and inwardly facing upper surface and being disposed in the corner recessed within said active-device region such that a center area of the bottom surface of the high aspect ratio contact opening remains free of said first conductive material;
• and
• a second conductive material deposited over said substantially ring-shaped structure and within said high aspect ratio contact opening.