Multiple line grids incorporating therein circuit elements
AssigneeGlotech Co., Ltd.
InventorChong Kwang Yoon
Life of this patent
Estimating the term…
Loading patent…
AssigneeGlotech Co., Ltd.
InventorChong Kwang Yoon
Estimating the term…
A multiple line grid (MLG) for use in a multiple line grid array(MLGA) packaging incorporates therein circuit elements, e.g., metal lines, resistors, capacitors, inductors, transistors or combinations thereof, with a view to reducing a size of a printed circuit board on which it is mounted. The MLGA package includes a semifinished package including a surface with a first metal pattern formed thereon for connecting a number of input/output terminals, a printed circuit board(PCB) including a top surface with a second metal pattern formed thereon according to the first metal pattern; and at least of a MLG which is disposed between the semifinished package and the PCB. The MLG includes a non-conductive body incorporated therein a plurality of circuit elements and multiple number of conductors in the form of a column. Each of the conductors is electrically isolated from each other and is electrically connected to the first and the second metal patterns.
A multiple line grid array package comprising
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
Leadless components: having an array of bottom contacts, e.g. pad grid array or ball grid array components
Reduction of cross-talk, noise or electromagnetic interference: using auxiliary mounted passive components or auxiliary substances
Vias, e.g. via plugs: through-vias
Structural association of two or more printed circuits: arrangements wherein electric components are disposed between and simultaneously connected…
Term ended 30 Nov 2019 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The present invention relates to an integrated circuit(IC) packaging; and, more particularly, to a multiple line grid array(MLGA) package including therein multiple line grids(MLGs), the MLGs incorporating therein circuit elements such as metal lines, resistors, inductors, capacitors, transistors or combinations thereof.
One of the most noticeable design trend in electronics industry nowadays is toward miniaturization through integration and densification of the circuit elements, and one of the technologies being developed to achieve this end is surface mount technology(SMT) which is being employed as a cost-effective means of mounting IC devices to printed circuit boards(PCBs). Numerous different techniques for mounting integrated circuit devices to circuit boards, chip carriers, or other components fall within the general category of SMT. Of these techniques, area array(as opposed to perimeter array) technology is often used to mount high I/O density packages with a great degree of reliability and manufacturing efficiency. Area array techniques include the use of pin grid array(PGAs), column grid arrays(CGAs), and ball grid arrays (BGAs). The more recent BGA and CGA techniques provide substantial improvements over PGA methods in that higher densities, reliability, and efficiency can be obtained for many types of packages.
As the name implies, ball grid arrays(BGAs) utilize a grid or array of electrical terminals, such as solder balls arranged on one side of the IC package to effectuate electrical contact with the circuit board The solder balls of the array may vary in material, size(height and width) and pitch(i.e., ball-to-ball spacing) according to the individual package. Additionally, the solder balls may be arranged in a uniform or a non-uniform array pattern, with some leads removed in certain areas, which is referred to as “depopulation”, depending on the desired attributes of the package. Solder balls are typically attached to the board or module using lead/tin eutectic solder balls, thereby allowing removal and rework without damage to the components
The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:
FIG. 1 is a perspective view of a conventional flip-chip type ball grid array package;
FIG. 2 shows a schematic cross-sectional view of one type of multiple line grid array package mounted on a printed circuit board in accordance with preferred embodiments of the present invention;
In FIG. 2, there is provided a schematic cross-sectional view of a multiple line grid array(MLGA) package 100 in accordance with preferred embodiments of the present invention, the MLGA package 100 mounted on a printed circuit board(PCB) 102 comprising an IC component 170 including a plurality of wire bonding pads 160, an array of multiple line grids(MLGs) 110 having a number of conductors 116, and a package substrate 120 formed by stacking a number of substrate layers for electrically connecting the IC component 170 to the array of MLGs 110.
The package substrate 120 is a non-conductive substrate provided with a top and a bottom surfaces, a first pattern formed on the bottom surface and a second pattern formed on the top surface. The first and the second patterns are designed in such a way that the wire bonding pads 160 of the IC component 170 are electrically connected to the array of MLGs 110 according to an input/output(I/O) terminal design.
The IC component 170 is mounted on top of the package substrate 120 by applying therebetween a polymeric adhesive 130 including therein, e.g., a silver paste and the like. Gold wires 140 are wire-bonded from the wire bonding pads 160 of the IC component 170 to metallization areas of the second pattern of the package substrate 120 for electrically connecting the array of MLGs 110 to the package substrate 120. The wire-bonded IC component 170 is encapsulated by a material such as a mold compound 150 in order to protect the IC component 170 from detrimental environmental effects such as moisture or the like.