Integrated circuit device having dual damascene capacitor

An integrated circuit device comprising:

• a semiconductor substrate;
• a dielectric layer, adjacent the semiconductor substrate, and having an opening therein, the dielectric layer comprising a lower dielectric layer portion adjacent the semicondutor substrate, an etch stop layer on the lower dielectric layer portion, and an upper dielectric layer portion on the etch stop layer, the opening having an upper portion in the upper dielectric layer portion and the etch stop layer, and a lower portion in the lower dielectric layer portion;
• and
• a capacitor comprising in stacked relation a lower electrode lining the opening, a capacitor dielectric layer adjacent the lower electrode, and an upper electrode adjacent the capacitor dielectric layer;
• the capacitor dielectric comprising in stacked relation a first metal oxide layer, a tantalum oxide layer, and a second metal oxide layer;
• the upper and lower metal electrodes comprising a metal nitride;
• and
• the capacitor having a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer.