Gate structure for integrated circuit fabrication
AssigneeAgere Systems Guardian Corp.
InventorsIsik C. Kizilyalli, Yi Ma, Sailesh Mansinh Merchant, Pradip Kumar Roy
Life of this patent
Estimating the term…
Abstract
The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.
Claims16
An integrated circuit, comprising:
- a substrate;
- a dielectric material layer disposed over said substrate, said dielectric material layer having an equivalent electrical thickness of 2.2 nm or less, and said dielectric material layer including a stress free oxide layer located on said substrate, a grown oxide layer located on said stress free oxide layer and a layer of high-k dielectric material located on said grown oxide layer;
- and
- an electrode disposed over said dielectric layer.
An integrated circuit, comprising:
- a substrate;
- a stress free oxide layer located over said substrate;
- a grown oxide layer located on said stress free oxide layer;
- at least one layer of high-k dielectric material disposed on said grown oxide layer;
- and
- an electrode disposed directly on said at least one layer of high-k dielectric material.
Dependencies are inferred from the claim text.