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US 6,320,235 B1Granted
Apparatus having low resistance angled implant regions
AssigneeMicron Technology, Inc.
InventorDavid F. Cheffings
Life of this patent
Estimating the term…
Abstract
The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried contact region with the source/drain region. The electrically conductive substrate interconnect is formed during an ion bombardment of the substrate wherein the ions enter the substrate at an oblique angle and underlie at least a portion of a region utilized to control the amount of ions entering the substrate.
Claims39
A semiconductor transistor, comprising:
- a gate formed over a substrate;
- a first source/drain region in the substrate, wherein the first source/drain region is adjacent the gate;
- a second source/drain region in the substrate, wherein the second source/drain region is adjacent the gate, further wherein the second source/drain region is physically separated from the first source/drain region;
- a buried contact region in the substrate, wherein the buried contact region is physically separated from the first source/drain region;
- and
- an electrically-conductive substrate interconnect, wherein the electrically-conductive substrate interconnect comprises an implanted region in the substrate interposed between the buried contact region and the first source/drain region, further wherein the electrically-conductive substrate interconnect provides electrical communication between the buried contact region and the first source/drain region.
3 more elements
A semiconductor memory device, comprising:
- an arrangement of memory cells;
- and
- at least one transistor associated with the arrangement of memory cells, wherein the at least one transistor comprises:
- a gate formed over a substrate;
- a first source/drain region in the substrate, wherein the first source/drain region is adjacent the gate;
- a second source/drain region in the substrate, wherein the second source/drain region is adjacent the gate, further wherein the second source/drain region is physically separated from the first source/drain region;
- a buried contact region in the substrate, wherein the buried contact region is physically separated from the first source/drain region;
- and
- an electrically-conductive substrate interconnect, wherein the electrically conductive substrate interconnect comprises an ion implanted region in the substrate interposed between the buried contact region and the first source/drain region, further wherein the electrically-conductive substrate interconnect provides electrical communication between the buried contact region and the associated source/drain region.
6 more elements
A semiconductor memory device, comprising:
- an arrangement of memory cells;
- and
- at least one transistor associated with the arrangement of memory cells, wherein the at least one transistor is formed using a method, comprising:
- forming a patterned control layer overlying a first area of a substrate, wherein the patterned control layer has an exposed edge, further wherein the exposed edge is substantially normal to a face plane of the substrate;
- conductively doping a second area of the substrate to form a first electrically-conductive region;
- conductively doping a third area of the substrate to form a second electrically-conductive region, wherein the second electrically-conductive region is physically separated from the first electrically-conductive region;
- and
- implanting ions in the first area of the substrate to form a third electrically-conductive region, wherein implanting ions comprises implanting ions at an implant angle, wherein the implant angle is between 0° and 90° relative to the exposed edge of the patterned control layer, further wherein a portion of the ions enter the exposed edge of the patterned control layer prior to implanting in the first area of the substrate, still further wherein the third electrically-conductive region provides electrical communication between the first electrically-conductive region and the second electrically-conductive region.
5 more elements
A semiconductor transistor, comprising:
- a gate formed over a silicon substrate having a first conductivity type;
- a first source/drain region having a second conductivity type and formed in the substrate, wherein the first source/drain region is adjacent the gate;
- a second source/drain region having the second conductivity type and formed in the substrate, wherein the second source/drain region is adjacent the gate, further wherein the second source/drain region is physically separated from the first source/drain region;
- a buried contact region having the second conductivity type and formed in the substrate, wherein the buried contact region is physically separated from the first source/drain region;
- and
- an electrically-conductive substrate interconnect having the second conductivity type, wherein the electrically-conductive substrate interconnect comprises an ion implanted region in the substrate interposed between the buried contact region and the first source/drain region, further wherein the electrically-conductive substrate interconnect provides electrical communication between the buried contact region and the first source/drain region;
- wherein the first conductivity type is selected from the group consisting of P-type and N-type;
- wherein the second conductivity type is the N-type when the first conductivity type is the P-type;
- and
- wherein the second conductivity type is the P-type when the first conductivity type is the N-type.
7 more elements
A semiconductor memory device, comprising:
- an arrangement of memory cells;
- and
- at least one transistor associated with the arrangement of memory cells, wherein the at least one transistor comprises:
- a gate formed over a silicon substrate having a first conductivity type;
- a first source/drain region having a second conductivity type and formed in the substrate, wherein the first source/drain region is adjacent the gate;
- a second source/drain region having the second conductivity type and formed in the substrate, wherein the second source/drain region is adjacent the gate, further wherein the second source/drain region is physically separated from the first source/drain region;
- a buried contact region having the second conductivity type and formed in the substrate, wherein the buried contact region is physically separated from the first source/drain region;
- and
- an electrically-conductive substrate interconnect having the second conductivity type, wherein the electrically-conductive substrate interconnect comprises an ion-implanted region in the substrate interposed between the buried contact region and the first source/drain region, further wherein the electrically-conductive substrate interconnect provides electrical communication between the buried contact region and the first source/drain region;
- wherein the first conductivity type is selected from the group consisting of P-type and N-type;
- wherein the second conductivity type is the N-type when the first conductivity type is the P-type;
- and
- wherein the second conductivity type is the P-type when the first conductivity type is the N-type.
10 more elements
A semiconductor memory device, comprising:
- an arrangement of memory cells;
- and
- at least one transistor associated with the arrangement of memory cells, wherein the at least one transistor is formed using a method, comprising:
- forming a patterned control layer overlying a first area of a silicon substrate having a first conductivity type, wherein the patterned control layer has an exposed edge, further wherein the exposed edge is substantially normal to a face plane of the substrate;
- conductively doping a second area of the substrate to form a first electrically-conductive region having a second conductivity type;
- conductively doping a third area of the substrate to form a second electrically-conductive region having the second conductivity type, wherein the second electrically-conductive region is physically separated from the first electrically-conductive region;
- and
- implanting ions in the first area of the substrate to form a third electrically-conductive region having the second conductivity type, wherein implanting ions comprises implanting ions at an implant angle, wherein the implant angle is between 0° and 90° relative to the exposed edge of the patterned control layer, further wherein a portion of the ions enter the exposed edge of the patterned control layer prior to implanting in the first area of the substrate, still further wherein the third electrically-conductive region provides electrical communication between the first electrically-conductive region and the second electrically-conductive region.
5 more elements
A semiconductor memory device, comprising:
- an arrangement of memory cells;
- and
- at least one transistor associated with the arrangement of memory cells, wherein the at least one transistor is formed using a method, comprising:
- forming a patterned control layer overlying a first area of a substrate, wherein the patterned control layer has an exposed edge, further wherein the exposed edge is substantially normal to a face plane of the substrate;
- conductively doping a second area of the substrate adjacent the exposed edge of the patterned control layer to form a buried contact region;
- implanting ions in the first area of the substrate to form an electrically-conductive substrate interconnect;
- removing a portion of the patterned control layer to expose a third area of the substrate;
- and
- conductively doping the third area of the substrate to form a source/drain region, wherein the source/drain region is physically separated from the buried contact region and wherein the electrically-conductive substrate interconnect is interposed between the buried contact region and the source/drain region.
6 more elements
A transistor, comprising:
- a gate formed over a well;
- a first source/drain region in the well, wherein the first source/drain region is adjacent the gate;
- a second source/drain region in the well, wherein the second source/drain region is adjacent the gate, further wherein the second source/drain region is physically separated from the first source/drain region;
- a buried contact region in the well, wherein the buried contact region is physically separated from the first source/drain region;
- and
- an electrically-conductive substrate interconnect, wherein the electrically-conductive substrate interconnect includes an ion-implanted region in the well interposed between the buried contact region and the first source/drain region, further wherein the electrically-conductive substrate interconnect provides electrical communication between the buried contact region and the first source/drain region.
3 more elements
A memory device, comprising:
- an arrangement of memory cells;
- and
- at least one transistor associated with the arrangement of memory cells, wherein the at least one transistor is formed using a method, comprising:
- forming a patterned control layer overlying a first area of a substrate having a first conductivity type, wherein the patterned control layer has an exposed edge, wherein the exposed edge is substantially normal to a face plane of the substrate;
- conductively doping a second area of the substrate to form a first electrically-conductive region having a second conductivity type;
- conductively doping a third area of the substrate to form a second electrically-conductive region having the second conductivity type, wherein the second electrically-conductive region is physically separated from the first electrically-conductive region;
- and
- implanting ions in the first area of the substrate to form a third electrically-conductive region having the second conductivity type, wherein implanting ions includes implanting ions at an implant angle, wherein the implant angle has a minimum of 60 degrees relative to the exposed edge of the patterned control layer, wherein a portion of the ions enter the exposed edge of the patterned control layer prior to implanting in the first area of the substrate, wherein the third electrically-conductive region provides electrical communication between the first electrically-conductive region and the second electrically-conductive region.
5 more elements
A memory device, comprising:
- an arrangement of memory cells;
- and
- at least one transistor associated with the arrangement of memory cells, wherein the at least one transistor is formed using a method, comprising:
- forming a polysilicon, patterned control layer overlying a first area of a substrate having a first conductivity type, wherein the patterned control layer has an exposed edge, wherein the exposed edge is substantially normal to a face plane of the substrate;
- conductively doping a second area of the substrate to form a first electrically conductive region having a second conductivity type;
- conductively doping a third area of the substrate to form a second electrically conductive region having the second conductivity type, wherein the second electrically-conductive region is physically separated from the first electrically-conductive region;
- and
- implanting ions in the first area of the substrate to form a third electrically conductive region having the second conductivity type, wherein implanting ions comprises implanting ions at an implant angle, wherein the implant angle is between 0° and 90° relative to the exposed edge of the patterned control layer, wherein a portion of the ions enter the exposed edge of the patterned control layer prior to implanting in the first area of the substrate, wherein the third electrically-conductive region provides electrical communication between the first electrically-conductive region and the second electrically-conductive region.
5 more elements
Dependencies are inferred from the claim text.