Semiconductor reliability test chip
AssigneeMicron Technology, Inc.
InventorsTim J. Corbett, Raymond P. Scholer, Fernando Gonzalez
Life of this patent
Estimating the term…
Abstract
A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.
Claims44
A semiconductor test chip having a plurality of test functions comprising:
- a semiconductor chip including a periphery having at least four sides, a plurality of contact pads located substantially adjacent at least a portion of at least one side of the periphery of the semiconductor chip, at least a portion of the plurality of contact pads being located in a first row and a second row located substantially adjacent behind the first row on at least a portion of at least one side of the semiconductor chip and at least a portion of one conductive line located substantially in a scribe area extending about at least a portion of the periphery of the semiconductor chip.
A semiconductor test chip having a plurality of test functions comprising:
- a semiconductor chip including a periphery formed by a plurality of sides, a plurality of contact pads located substantially adjacent a portion of the periphery of the semiconductor chip, the plurality of contact pads forming a plurality of groups of contact pads extending substantially about at least a portion of at least one side the periphery of the semiconductor chip, each group of the plurality of groups of contact pads including at least a first row of contact pads and at least a second row of contact pads located adjacent the first row of contact pads, a portion of the plurality of contact pads including active circuitry of the semiconductor chip.
Dependencies are inferred from the claim text.