Sub-nanoscale electronic devices and processes
AssigneesYale University, University of South Carolina
InventorsMark A. Reed, James M. Tour
Life of this patent
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Abstract
An integrated circuit structure including a plurality of transistors; a plurality of thin-film conductor interconnects, interconnected to form electronic circuits in a predetermined electrical configuration; and a plurality of pairs of contact pads, connected to the thin-film conductor interconnects, each adjacent pair of contact pads including a first pad of a first conductive material and a second pad of a second conductive material, and being electrically connected only by a conductive oligomer of a precisely determined number of units.
Claims4
A process for manufacturing integrated circuits, comprising the steps of:
- a.) providing a substrate;
- b.) forming a plurality of transistors on said substrate;
- c.) forming conductive interconnects on said substrate to interconnect said transistors in a predetermined electrical configuration;
- d.) forming, among said interconnects, pairs of conductive contact pads;
- and
- e.) through a process of self-aligned spontaneous assembly of chemically synthesized interconnects, forming polymeric conductors to electrically connect respective pairs of conductive pads.
Dependencies are inferred from the claim text.