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US 6,319,859 B1Granted
Borderless vias with HSQ gap filled metal patterns having high etching resistance
AssigneeAdvanced Micro Devices, Inc.
InventorKhanh Q. Tran
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Abstract
Spacings between metal features are gap filled with HSQ. Portions of the deposited HSQ adjoining the side surfaces and upper surface of a metal feature are selectively heated to increase the density and etch resistance of the adjoining HSQ portions, thereby enabling formation of reliable, voidless, low resistance, borderless vias. In an embodiment of the present invention, selective heating is effected by heating a metal line to indirectly heat the adjoining portions of the HSQ layer, as by infrared heating.
Claims17
A method of manufacturing a semiconductor device, which method comprises:
- forming a first conductive feature having an upper surface and side surfaces;
- depositing a layer of hydrogen silsesquioxane (HSQ) on the upper surface and side surfaces of the first conductive feature;
- and
- selectively heating portions of the HSQ layer adjoining the upper and side surfaces of the first conductive feature to increase the density and etching resistance of the selectively heated adjoining portions of the HSQ layer above the density and etching resistance of portions of the HSQ layer which do not adjoin the first conductive feature.
1 more element
Dependencies are inferred from the claim text.