Method of manufacturing semiconductor device with via holes reaching interconnect layers having different top-surface widths

A method of manufacturing a semiconductor device, comprising steps of:

• forming a first interconnect layer and a second interconnect layer on a substrate, said second interconnect layer having a second top surface area that is larger than a first top surface area of said first interconnect layer;
• forming a hydrogen silsesquioxane film on said first interconnect layer and said second interconnect layer;
• forming an insulating layer on said hydrogen silsequioxane film;
• and
• etching said insulating layer and said hydrogen silsesquioxane film to form a first via hole reaching said first top surface area and a second via hole reaching said second top surface area;
• wherein said etching step is performed using a mixture of etching gas under a condition, such that a first etching rate of said hydrogen silsesquioxane film and a second etching rate of said insulating layer are about the same.

A method of manufacturing a semiconductor device comprising steps of:

• forming a first interconnect layer and a second interconnect layer on a substrate, said second interconnect layer having a second top surface area that is larger than a first top surface area of said first interconnect layer;
• forming a hydrogen silsesquioxane film on said first interconnect layer and said second interconnect layer;
• forming an insulating layer on said hydrogen silsesquioxane film;
• and
• etching said insulating layer and said hydrogen silsesquioxane film to form a first via hole reaching said first top surface area and a second via hole reaching said second top surface area;
• wherein said etching step is performed using a mixture of etching gas under a condition, such that a first etching rate of said hydrogen silsesquioxane film and a second etching rate of said insulating layer are about the same, said mixture comprising C4F8,Ar, O2, CO and H2.