Approach to form an inter-polysilicon oxide (IPO) layer for charge coupled devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWen-Cheng Chien, Jen-Pan Wang
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Abstract
A method for forming an IPO between two polysilicon layers that produces an oxide of superior uniformity and eliminates undercutting, stringer formation, fringe electric fields and plasma damage. The method modifies the prior art by using a densified TEOS mask to allow etching away of the substrate oxide and allow the selective etch of a subsequent non-densified TEOS layer. A high temperature thermal oxide (HTO) then covers the resulting formation. The thickness of the second TEOS layer can be controlled to prevent field fringing and the underlying HTO layer prevents undercutting and stringer formation.
Claims22
A method for forming an inter-polysilicon oxide (IPO) layer between two polysilicon layers (POLY1 and POLY2) deposited on a certain silicon substrate in a microelectronics fabrication in such a manner that the deposition of POLY2 layer does not undercut the previously deposited IPO layer, comprising:
- providing a silicon substrate on which has been formed an oxide-nitride-oxide (ONO) layer, by a succession of thermal depositions consisting of a deposited high temperature silicon oxide (HTO) layer over which has been deposited a silicon nitride layer over which has been deposited a high temperature silicon oxide (HTO) layer;
- depositing on said substrate a first polysilicon layer (POLY1) or a topographic distribution of such layers;
- depositing on said polysilicon layers, using a dry etch, a mask of densified tetraethyl orthosilicate (TEOS);
- subjecting said fabrication of TEOS-masked polysilicon layers to a wet dip for removal of the outer thermal oxide (HTO) layer on the silicon substrate;
- depositing on said fabrication a non-densified layer of tetraethyl orthosilicate (TEOS);
- subjecting said fabrication to a partial dry etch followed by a partial HF wet etch;
- depositing on said fabrication a high temperature thermal oxide (HTO) and
- depositing over said high temperature thermal oxide on said fabrication a second polysilicon layer (POLY2).
A method for forming an inter-polysilicon oxide (IPO) layer with end-caps whose width can be controlled during fabrication to eliminate electric field fringing in microelectronic devices, comprising:
- providing a silicon substrate on which has been formed an oxide-nitride-oxide (ONO) layer, by a succession of thermal depositions consisting of a deposited high temperature silicon oxide (HTO) layer over which has been deposited a silicon nitride layer over which has been deposited a high temperature silicon oxide (HTO) layer;
- depositing on said substrate a first polysilicon layer (POLY1) or a topographic distribution of such layers;
- depositing on said polysilicon layers, using a dry etch, a mask of densified tetraethyl orthosilicate (TEOS);
- subjecting said fabrication of TEOS-masked polysilicon layers to a wet dip for removal of the outer thermal oxide (HTO) layer on the silicon substrate;
- depositing on said fabrication a non-densified layer of tetraethyl orthosilicate (TEOS);
- subjecting said fabrication to a partial dry etch followed by a partial HF wet etch to remove a portion of said non-densified layer of tetraethyl orthosilicate (TEOS) and form lateral end-caps, wherein the duration of said dry and wet etches allow control of the lateral thickness of the remaining end-cap portion of the layer of non-densified tetraethyl orthosilicate (TEOS);
- depositing on said fabrication a high temperature thermal oxide (HTO) and depositing over said high temperature thermal oxide on said fabrication a second polysilicon layer (POLY2).
Dependencies are inferred from the claim text.