Method and apparatus for improved planarity metallization by electroplating and CMP
AssigneeAdvanced Micro Devices, Inc.
InventorsDarrell M. Erb, Steven C. Avanzino, Fei Wang
Life of this patent
Estimating the term…
Abstract
A pattern of in-laid conductors is formed by a method utilizing electroplating and chemical-mechanical polishing (CMP). Embodiments include a first step of selectively filling recesses formed in the surface of a substrate with a metal by localized electroplating at a reduced thickness, planar-surfaced overburden or blanket layer thereon, and planarizing the surface by CMP utilizing a relatively soft CMP pad. Embodiments also include an apparatus comprising a porous pad applicator for selectively electroplating recesses formed in the surface of a workpiece.
Claims18
A method of forming a layer of an electrically conductive material filling a plurality of spaced-apart recesses of different widths and depths formed in a substrate surface, said layer having an exposed upper surface substantially co-planar with said substrate surface, which method comprises the sequential steps of:
- providing a substrate having an exposed upper surface comprising a plurality of spaced-apart recesses of different depths formed therein and a plurality of non-recessed areas therebetween, said plurality of recesses including at least one relatively wide recess and at least one relatively narrow recess;
- performing a first, selective plating process for selectively substantially filing and plurality of recesses with said electrically conductive material while leaving said plurality of non-recessed areas of said upper surface of said substrate unplated;
- performing a second plating process for forming a predetermined thickness overburden layer of said electrically conductive material over said upper surface of said substrate, the exposed upper surface of said overburden layer being generally planar;
- and
- chemical-mechanical polishing said exposed upper surface of said overburden layer to (a) substantially remove the portions thereof covering said non-recessed areas of said upper surface of said substrate and (b) render the exposed upper surfaces of the portions of said electrically conductive material filling said recesses substantially co-planar with said non-recessed areas of said upper surface of said substrate.
A method of manufacturing a semiconductor device, which method comprises the sequential steps of:
- providing a substrate comprising a semiconductor wafer having thereon a dielectric layer with an exposed upper surface comprising a plurality of spaced-apart recesses of different widths and depths formed therein, with non-recessed areas therebetween;
- performing a first, selective electroplating process for selectively substantially filling the plurality of recesses with a layer of copper or an alloy thereof while leaving said non-recessed areas of said upper surface of said substrate unplated;
- performing a second plating process for forming a predetermined thickness overburden layer of copper or an alloy thereof over said upper surface of said substrate, the exposed upper surface of said overburden layer being generally planar;
- and
- chemical-mechanical polishing said exposed upper surface of said copper or copper alloy overburden layer to (a) substantially remove the portions thereof covering said non-recessed areas of said upper surface of said substrate and render exposed upper surfaces of said copper or copper alloy layer filling said recesses substantially co-planar with said non-recessed areas of said upper surface of said substrate.
Dependencies are inferred from the claim text.