Enhanced interconnection to ceramic substrates

#This invention relates to integrated circuit construction and, more particularly, to an enhanced interconnection to ceramic substrates of a semiconductor chip or printed circuit board.

#The evolution of electrical and electronic circuitry from component circuits to integrated circuits, particularly microelectronic integrated circuits, has presented various new considerations in circuit design. Among these considerations is the necessity of connecting circuits on the semiconductor chip to other chips or devices mounted on a printed circuit board. This is because not all connections can be made inside a single chip. Therefore, it is necessary to connect externally to different I/O areas with external conductors, such as wires. Likewise, power must be supplied to the semiconductor chips.

#In order to eliminate use of wiring, chip carriers have found widespread use. The chip carrier consists of a substrate having I/O pads on either side with internal connections between the I/O pads. Referring to FIG. 1, an exemplary such prior art integrated circuit is illustrated with a semiconductor chip 10, a chip carrier 12, and a printed circuit board 14. The chip 10 is connected to I/O pads of the chip carrier 12 using, for example, solder balls 16. Likewise, opposite I/O pads of the chip carrier 12 are connected to the board using solder balls 16. As is known, interconnections can also be provided by controlled collapsible chip connectors (C4s), columns, pins or the like. The solder balls 16 on either side of the chip carrier 12 are formed in an array corresponding to the location of the I/O pads. This construction is conventionally referred to as a ball grid array (BGA). Although not shown, the chip carrier 12 may be modified to include pins brazed to the I/O pads for connection to the board 14 to define a pin grid array (PGA).

#FIG. 1 is a side elevation view of a prior art integrated circuit;

#FIG. 2 is a partial sectional view of a semiconductor chip interposer according to the invention;

#FIG. 3 is a side elevation view of an integrated circuit single chip module, similar to FIG. 1, including the interposer of FIG. 2 illustrated in section;

#With reference to FIG. 2, a semiconductor chip interposer 20 according to the invention is illustrated. The interposer 20 is adapted to distribute mismatches of thermal coefficients of expansion (TCE) between various components in an integrated circuit, such as that shown in FIG. 1 and discussed above. Particularly, interconnection between, for a ceramic chip carrier and board interconnection is accomplished using a thin interposer which has a thermal coefficient of expansion intermediate the TCE of the ceramic chip carrier and the TCE of the board. As an example, if the ceramic chip carrier has a TCE of 3 ppm/° C. and the board has a TCE of 19 ppm/° C., as discussed relative to FIG. 1, then the interposer will have a TCE in the range of about 10-14 ppm/° C.

#The interposer 20 comprises a thin metal plate 22 having through openings or via holes 24 through the plate 22. The via holes 24 may be formed in any known manner, such as drilling, etching, etc. The via holes 24 are patterned according the bottom surface metallurgy (BSM) of the corresponding component with which it will be used. The metal plate 22 may be, for example, stainless steel, nickel, aluminum, Ti, Ti—Al, Ti—Al—V, or the like. The thickness of the plate 22 should be greater than 2 mils. For example, the plate 22 might be a metal foil in the range of 2-8 mil thickness.

#To provide insulation between via holes 24, an insulation coating 26 is provided on the plate 22, including on walls of the via holes 24. Advantageously, the insulation coating 26 comprises an oxide coating. The oxide coating 26 may be a thermally grown oxide or be formed by anodization. Using conventional masking technology, the via holes 24 with the insulation coating 26 are filled with an electrical conductive material 28 and to form I/O pad 30 on both sides. The via conductive material 28 and the I/O pads 30 may be formed, for example, of materials such as Cu, Cu—Ni, Ni, Ag, Au or Pd.