Method for manufacturing a chip scale package having copper traces selectively plated with gold
AssigneeSamsung Electronics Co., Ltd.
InventorsDo Soo Jeong, Hai Jeong Sohn, Dong Ho Lee
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AssigneeSamsung Electronics Co., Ltd.
InventorsDo Soo Jeong, Hai Jeong Sohn, Dong Ho Lee
Estimating the term…
A method for manufacturing a chip scale package comprises preparing a tape wiring board that includes a polyimide tape having top and bottom surfaces, Cu traces formed on the bottom surface of the tape, a window formed in the tape to enable the Cu traces to be connected to a semiconductor chip attached below the board, multiple connection holes formed in the tape to expose portions of the Cu traces therethrough and define solder ball mounting pads, and an elastomer chip carrier attached to the bottom surface of the tape. The method includes applying either a pre-flux or a cover sheet over the solder ball mounting pads. The pre-flux and the cover sheet each prevents the solder ball mounting pads being plated with gold. This, in turn, prevents the formation of intermetallic compounds in the solder balls so that the bond strength between the solder balls and a pad to which they attach is improved.
A method for manufacturing a chip scale package, the method comprising:
A method for manufacturing a chip scale package, the method comprising:
A method for manufacturing a chip-scale package, comprising:
Dependencies are inferred from the claim text.