Process for forming a borderless via in a semiconductor device

A process for forming a borderless via in a semiconductor device, comprising:

• providing a dielectric layer;
• forming a conductive layer and a borophosphosilicate glass (BSG) layer over the dielectric layer in sequence;
• forming a patterned first photoresist mask layer to cover the borophosphosilicate glass layer;
• performing a first etching process to pattern the borophosphosilicate glass layer into a borophosphosilicate glass plug while using the patterned first mask layer as a mask;
• forming a second photoresist mask layer to cover the patterned first mask layer and the conductive layer;
• performing a second etching process to pattern the conductive layer using the patterned first mask layer and the second photoresist mask layer as an etching mask in order to form a conductive line beneath the borophosphosilicate glass plug and the second mask layer;
• removing the first photoresist mask layer and second photoresist mask layer;
• forming an inter-metal dielectric layer around the borophosphosilicate glass plug and the conductive line;
• removing the borophosphosilicate glass plug to form a borderless via in the inter-metal dielectric layer;
• and
• filling the borderless via with a barrier layer and a metal layer to form a metal plug.