Process to separate the doping of polygate and source drain regions in dual gate field effect transistors

A method of forming a semiconductor device, comprising the steps of:

• a) providing a substrate having an insulating layer formed thereon;
• b) forming a gate stack formed over said substrate, said gate stack having:
• (i) a first gate material layer doped with a first dopant at a first doping level;
• (ii) a first conducting layer comprised of a conducting material capable of surviving thermal processing;
• and
• (iii) a blocking layer thicker than about 1000 Å;
• c) forming heavily doped source-rain regions in said substrate, said heavily doped source-drain regions in said substrate doped with a second dopant at a second doping level, said dopant introduced at an energy of about 40 KeV;
• d) forming a second conducting layer over said heavily doped source-drain regions;
• and
• e) performing an activation cycle comprising heating said substrate to at least approximately 1000° C.

A method of forming a semiconductor device, comprising the steps of:

• a) providing a substrate having isolation regions;
• b) forming an insulating layer over said substrate;
• c) forming a polysilicon layer over said substrate;
• d) doping said polysilicon layer with a first dopant at a first doping level;
• e) forming a first conducting layer over said polysilicon layer with a conducting material capable of surviving an activation cycle;
• f) forming a blocking layer over said first conducting material layer, said blocking layer having a thickness of about 1000 Å;
• g) etching said blocking layer, said first conducting layer, and said polysilicon layer to form a gate stack and to define source-drain regions;
• h) doping said source-drain regions with a second dopant at a second doping level to form heavily doped source-drain regions;
• and
• i) forming a second conducting layer over said heavily doped source-drain regions.

In forming a semiconductor device having a gate and source-drain regions, a method for independently doping the gate and the source-drain regions, comprising the steps of:

• a) providing a substrate having isolation regions;
• b) forming a thin oxide insulating layer over said substrate;
• c) forming a polysilicon layer over said thin insulating layer;
• d) introducing into said polysilicon layer a first dopant at a first doping level;
• e) forming a WSi or TiN layer over said polysilicon layer;
• f) forming an oxide blocking layer having a thickness of about 1000 Å over said WSi or TiN layer sufficient to prevent dopant penetration into said layer formed in step (e);
• g) etching said oxide blocking layer, said WSi or TiN layer, and said polysilicon layer to form a gate stack and to define source-drain regions;
• h) forming a protective oxide layer around said gate stack;
• i) introducing into said source-drain regions and not into said polysilicon layer a second dopant at a second doping level;
• j) exposing said substrate to a temperature of at least approximately 1000° C.;
• k) forming oxide spacers abutting said gate stack and having a height that reaches to at least the top of said WSi or TiN layer;
• l) forming a TiSi2 layer over said source-drain regions;
• m) forming a top oxide overlayer over said gate stack and said source-drain regions;
• n) forming contacts with said WSi or TiN layer and said TiSi2 layer.