Method for reducing lateral dopant gradient in source/drain extension of MOSFET
AssigneeAdvanced Micro Devices, Inc.
InventorBin Yu
Life of this patent
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Abstract
A method for reducing lateral dopant gradient diffusion in the source/drain extension (SDE) region of a MOSFET includes forming the deep source and drain using high temperature dopant activation annealing, and then implanting a preamorphization species in an amorphized extension region that is to become the SDE region. Then, both SDE dopant and, if desired, halo dopant are implanted into the amorphized extension region and activated using relatively low temperature annealing, thereby reducing the thermal budget of the process and concomitantly reducing unwanted dopant thermal diffusion.
Claims15
A method for establishing at least one transistor on a semiconductor device, comprising:
- providing a semiconductor substrate;
- implanting source and drain dopants into the substrate to establish a source region and a drain region;
- heating the substrate to activate the dopants;
- then
- implanting at least one neutral ion species in the substrate between the source and drain regions to define an amorphous extension region;
- implanting at least a source/drain extension (SDE) dopant in the amorphous extension region;
- and
- heating at least the amorphous extension region to activate the SDE dopant.
A method for making an ultra-large scale integration (ULSI) semiconductor device, comprising:
- establishing source and drain regions in a semiconductor substrate using a first activation temperature;
- then
- establishing a doped source/drain extension (SDE) region between the source and drain regions using a second activation temperature less than the first activation temperature.
Dependencies are inferred from the claim text.