Method for improved processing and etchback of a container capacitor
AssigneeMicron Techonology, Inc.
InventorRobert K. Carstensen
Life of this patent
Estimating the term…
Abstract
A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.
Claims36
A method for fabricating an integrated circuit capacitor comprising:
- forming a container opening in a first insulating layer formed over a substrate;
- forming an oxide layer over said substrate in said container opening;
- forming a conductive plug over said oxide layer;
- forming a second insulating lacer over said conductive plug and said first insulating layer;
- etching said second insulating layer such that the space formed in said second insulating layer is wider than said plug;
- removing said plug and said oxide layer to form a container opening;
- forming a first conductive layer in said container opening over an active area of said substrate;
- forming a first dielectric layer atop said first conductive layer;
- and
- forming a second conductive layer atop said dielectric layer.
A method for fabricating a DRAM cell container capacitor comprising:
- forming a container opening in a first insulating layer formed over a substrate;
- forming an oxide layer over said substrate;
- forming a plug over said oxide layer;
- forming a second insulating layer over said plug and said first insulating layer;
- etching said second insulating layer such that the space formed in said second insulating layer is larger than said plug;
- removing said plug, and said oxide layer to form a container opening;
- forming a first conductive layer in said container opening over an active area of said substrate;
- forming a first dielectric layer atop said first conductive layer;
- and
- forming a second conductive layer atop said dielectric layer.
A method for fabricating an integrated circuit capacitor comprising:
- providing a first insulating layer over a substrate;
- forming a first opening in said first insulating layer;
- partially filling said first opening with a conductive material;
- providing a second insulating layer over said first insulating layer and said conductive material;
- forming a second opening in said second insulating layer which has a greater width than said first opening;
- removing said conductive material from said first opening;
- forming a first conductive layer over said first and second openings;
- forming a dielectric layer over said first conductive layer;
- and
- forming a second conductive layer over said dielectric layer.
A method for fabricating an integrated circuit capacitor comprising:
- providing a first insulating layer over a substrate;
- forming a first opening in said first insulating layer;
- providing a second insulating layer over said first insulating layer after forming said first opening and without filling said first opening with said second insulating layer;
- forming a second opening in said second insulating layer which has a greater width than said first opening;
- forming a first conductive layer over said openings, wherein said first conductive layer is in direct contact with an active area in said substrate;
- forming a dielectric layer over said first conductive layer;
- and
- forming a second conductive layer over said dielectric layer.
Dependencies are inferred from the claim text.