US 6,319,779 B1 · Semiconductor transistor devices and methods for forming semiconductor transistor devices

Abstract

The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate. The invention also includes a semiconductor transistor device comprising: a) a region of a semiconductor material wafer; b) a transistor gate over a portion of the region of the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) opposing source/drain regions operatively adjacent the transistor gate, each source/drain region having an inner lateral boundary; d) opposing sidewall spacers adjacent the sidewalls of the transistor gate, each sidewall spacer having an outer lateral edge, the sidewall spacers and source/drain regions being paired such that the outer lateral edges of the sidewall spacers are displaced laterally inwardly relative to the inner lateral boundaries of the source/drain regions; and e) lateral gaps, the lateral gaps extending from the outer lateral edges of the sidewall spacers to the inner lateral boundaries of the source/drain regions.

Claims2

Dependent claims

A method for forming a peripheral NMOS transistor and one or more memory NMOS transistors, the method comprising the following steps:

forming a peripheral NMOS transistor gate and one or more memory NMOS transistor gates;
forming source/drain regions, halo regions and LDD regions operatively adjacent the peripheral NMOS transistor gate, and forming source/drain regions operatively adjacent the one or more memory NMOS transistor gates, the steps of forming the regions occurring in a sequence such that one or more of the regions are formed last and are therefore last formed regions, wherein the LDD regions formed operatively adjacent the peripheral NMOS transistor gate are not the last formed regions;
forming sidewall spacers adjacent the peripheral NMOS transistor gate subsequent the forming of the LDD regions operably adjacent peripheral NMOS transistor gate, the sidewall spacers being formed to have a first width;
reducing the first width after the forming of the source/drain regions;
and
wherein less than two masking layer provision steps are employed after the formation of the LDD regions operatively adjacent the peripheral NMOS transistor gate, and prior to formation of the one or more last formed regions.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor transistor devices and methods for forming semiconductor transistor devices

Life of this patent

Semiconductor transistor devices and methods for forming semiconductor transistor devices

Life of this patent

Abstract

Claims2