A computer-readable memory storing gated clock design supporting program, said gated clock design supporting program comprising the steps of:
- inputting information about a logic circuit not clock-gated, information about enable logic for controlling a clock output and information about a gating circuit;
- generating a timing constraint to be secured for said enable logic;
- calculating a delay time in said enable logic;
- determining whether or not said enable logic satisfies said timing constraint based on said delay time;
- when said enable logic satisfies said timing constraint, adding said gating circuit and a circuit composed of said enable logic to said logic circuit not clock-gated so as to generate a clock-gated logic circuit;
- and
- outputting information about said clock-gated logic circuit and said timing constraint to be secured for said enable logic.