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US 6,317,948 B1Granted
Embedded thin film passive components
AssigneeAgere Systems Guardian Corp.
InventorsRatnaji Rao Kola, Louis Thomas Manzione, Roderick Kent Watts
Life of this patent
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Abstract
The specification describes of multilevel printed circuit boards and a process for their manufacture in which capacitors and other passive components are buried between levels of the multilevel board. The capacitor in the multilevel structure is designed so that access is conveniently provided to connect from the parallel plate electrodes of the interlevel capacitor to the board surface or to another board level using plated through hole interconnects.
Claims11
A method for the manufacture of a multi-level printed circuit board comprising the steps of:
- a. depositing a first metal layer on the surface of a first printed circuit board level,
- b. patterning said first layer to form a first planar capacitor electrode,
- c. forming a dielectric layer over the first planar electrode,
- d. depositing a second metal layer over the dielectric layer,
- e. patterning said second metal layer to form a second planar electrode, said second planar electrode covering said dielectric layer except for a portion of said insulating layer remaining uncovered, said portion of said insulating layer remaining uncovered providing a first interconnection region, said second planar electrode having an additional portion extending laterally beyond said insulating layer, said additional portion of said second planar electrode providing a second interconnection region,
- f. adhesively bonding a second printed circuit board level to the surface of said first printed circuit board level thereby producing a multi-level printed circuit board, with said first and second planar electrodes, and said dielectric layer buried between said first and second printed circuit board levels,
- g. forming through holes through at least said second printed circuit board level with a first through hole through said first interconnection region and a second through hole through said second interconnection region, and
- h. coating said through holes with metal to form electrical contacts to said first and second planar electrodes.
5 more elements
Dependencies are inferred from the claim text.