Viterbi decoder
AssigneeSamsung Electronics Co., Ltd.
InventorsSung-han Choi, Jun-jin Kong
Life of this patent
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Abstract
An apparatus for providing and storing a state metric which is used for an add-compare-select (ACS) operation in a Viterbi decoder using a number of ACS units in order to enhance decoding speed. A state metric memory in Viterbi decoder uses a two-port memory, in which a memory bank for reading and writing a state metric of a first half among the N state metrics generated in a ACS unit and two memory banks for alternately reading and writing the state metric of the second half whenever a codeword is input, are incorporated into a single memory. As a result, the storage capacity for storing the state metrics can be greatly reduced as compared to a conventional apparatus.
Claims4
A Viterbi decoder comprising:
- a branch metric calculator for calculating a similarity between an input codeword and a predetermined codeword which can be output from an encoder and outputting 2N branch metrics where N is the number of states;
- an add-compare-select (ACS) portion for performing an add-compare operation by receiving 2N branch metrics and N previous state metrics provided from the branch metric calculator, selecting a survival path showing an encoding sequence closest to that of the received codeword, and calculating N current state metrics;
- and a state metric memory for providing the N previous state metrics to the ACS unit or storing the N current state metrics generated by the ACS unit;
- wherein
- said ACS unit comprises M ACS units each of which perform N/M operations during N/M cycles whenever a codeword is input;
- and
- said state metric memory comprises:
- a memory including a memory bank for reading and writing a state metric of the first half among the N state metrics generated in said ACS unit, and two memory banks for alternately reading and writing the state metrics of the second half whenever a codeword is input;
- a counter for counting a preceding sequence of said cycles;
- a write address generator for generating a write address of said memory based on the count result of said counter;
- and
- a read address generator for generating a read address of said memory based on the count result of said counter.
Dependencies are inferred from the claim text.