Clock recovery using an injection tuned resonant circuit

A clock recovery cell, comprising:

• an LC tank circuit comprising an inductor and a capacitor, said LC tank circuit tuned to a data signal and adapted to output a recovered clock signal;
• a negative resistance in parallel with at least one of said inductor and said capacitor;
• and
• an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow infection of said data signal into said LC tank circuit;
• wherein a representation of said data signal is infected into each of at least two nodes of said clock recovery cell, each of said representations of said data signal is phase shifted from another of said representations of said data signal.

A clock recovery cell, comprising:

• an LC tank circuit comprising an inductor and a capacitor, wherein said LC tank circuit is outside a loop of said phase locked loop;
• a negative resistance in parallel with at least one of said inductor and said capacitor;
• an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of said data signal into said LC tank circuit;
• said phase locked loop adapted to provide a frequency control signal;
• and
• at least one component in said LC tank circuit being adjustable under a control of said frequency control signal.

A clock recovery cell, comprising:

• an LC tank circuit comprising an inductor and a capacitor;
• a negative resistance in parallel with at least one of said inductor and said capacitor;
• and
• an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of said data signal into said LC tank circuit;
• a phase locked loop adapted to provide a frequency control signal, wherein said phase locked loop comprises a second LC tank circuit;
• and
• at least one component in said LC tank circuit being adjustable under a control of said frequency control signal.

A clock recovery cell, comprising:

• an LC tank circuit comprising an inductor and a capacitor;
• a negative resistance in parallel with at least one of said inductor and said capacitor;and
• an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal into said LC tank circuit;
• and
• a directional coupler between said data signal and said LC tank circuit to limit a signal flow back from said LC tank circuit;
• wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal.

Apparatus for recovering a clock signal from a data signal, comprising:

• means for injecting a signal corresponding to said data signal into an oscillator circuit;
• means for tuning said oscillator circuit to said data signal;
• means for outputting said clock signal from said oscillator circuit wherein said means for tuning tunes said oscillator circuit to a frequency corresponding to approximately a data rate of said data signal;
• and
• means for injecting a phase-shifted representation of said data signal into said oscillator circuit.

An apparatus for recovering a data clock signal from a data signal according comprising:

• means for injecting a signal corresponding to said data signal into an oscillator circuit;
• means for tuning said oscillator circuit to said data signal, wherein said means for tuning tunes said oscillator circuit to a frequency corresponding to a fraction of a data rate of said data signal;
• and
• means for outputting said clock signal from said oscillator circuit wherein said means for tuning tunes said oscillator circuit to a frequency corresponding to approximately a data rate of said data signal.

An apparatus for recovering a data clock signal from a data signal comprising:

• means for injecting a signal corresponding to said data signal into an oscillator circuit;
• means for tuning said oscillator circuit to said data signal;
• means for outputting said clock signal from said oscillator circuit wherein said means for tuning tunes said oscillator circuit to a frequency corresponding to approximately a data rate of said data signal;
• and
• means for infecting a phase-shifted representation of said data signal into said oscillator circuit, wherein said phase-shifted representation of said data signal is shifted 180° with respect to said data signal.

A data communication device, comprising:

• a modem;
• and
• a tuned oscillator, said tuned oscillator comprising:
• an LC tank circuit comprising an inductor and a capacitor, and
• an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal and adapted to output a recovered clock signal;
• wherein said tuned oscillator is tuned to a frequency corresponding to approximately a data rate of said data signal.

A clock recovery cell, comprising:

• an LC tank circuit outside a loop of a phase locked loop comprising an inductor and a capacitor;
• said phase locked loop adapted to provide a frequency control signal;
• at least on component in said LC tank circuit being adjustable under a control of said frequency control signal;
• an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal into said LC tank circuit;
• and
• wherein said LC tank circuit is adapted to be tuned to a frequency corresponding to approximately a data rate of said data signal and is adapted to output a recovered clock signal.

A method of recovering a clock signal from a data signal, comprising:

• injecting a data signal corresponding to said clock signal into an oscillator circuit;
• tuning said oscillator circuit to said data signal;
• and
• outputting said clock signal from said oscillator circuit wherein said oscillator circuit is tuned to a frequency corresponding to approximately ½ of a data rate of said data signal.

A clock recovery cell, comprising:

• an LC tank circuit comprising an inductor and a capacitor;
• an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal into said LC tank circuit, wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal;
• and
• a first flip/flop clocked by a recovered clock signal output from said LC tank circuit.

A clock recovery cell, comprising:

• an LC tank circuit comprising an inductor and a capacitor;
• an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal into said LC tank circuit wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal;
• and
• a directional coupler between said data signal and said LC tank circuit to limit a signal flow back from said LC tank circuit.

A clock recovery cell, comprising:

• an LC tank circuit comprising an inductor and a capacitor;
• an impedance in communication with said LC tank circuit, said impedance being adapted and arranged to allow injection of a data signal into said LC tank circuit wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal;
• and
• a representation of said data signal phase shifted from another of said representations of said data signal injected into each of at least two nodes of said clock recovery cell.

A clock recovery cell, comprising:

• an LC tank circuit comprising an inductor and a capacitor;
• and
• an impedance connected to a node between said inductor and said capacitor, said impedance adapted and arranged to allow injection of a data signal into said LC tank circuit;
• wherein said LC tank circuit is tuned to said data signal and is adapted to output a recovered clock signal.