Generalized address generation for bit reversed random interleaving
AssigneeQUALCOMM Incorporated
InventorsAvneesh Agrawal, Qiuzhen Zou
Life of this patent
Estimating the term…
Abstract
A novel and improved method and apparatus for address generation in an interleaver is provided. In accordance with one embodiment of the invention, an address is generated using a random address fragment and a bit reversed address fragment. The bit reversed address fragment is selected by first generating two consecutive candidate bit reversed fragments. The second bit reversed address fragment is selected when the first bit reversed address fragment generates an address that is greater than a maximum address. The address generator allows address generation for interleaver and deinterleaver frame sizes of N, where N is not an integer power of two, without any cycle penalty.
Claims8
An interleaver, having a size N where N is not an integer power of two, comprising:
- means for generating a current bit reversed address fragment;
- means for generating a next bit reversed address fragment;
- means for generating a pseudo random address fragment;
- means for generating a next pseudo random address fragment;
- and
- a control unit that selects:
- the current bit reversed address fragment when an address made of the current bit reversed address fragment and the pseudo random address fragment is not greater than N,
- the next bit reversed address fragment when greater than N, and
- the next pseudo random address fragment when the next bit reversed address fragment is identified as being a first address in a bit reversed address fragment series.
An interleaver, having a size N where N is not an integer power of two, comprising:
- means for generating a current bit reversed address fragment;
- means for generating a next bit reversed address fragment;
- means for generating a pseudo random address fragment;
- and
- a control unit that selects:
- the current bit reversed address fragment when an address made of the current bit reversed address fragment and the pseudo random address fragment is not greater than N,
- and the next bit reversed address fragment when greater than N, the current bit reversed address fragment and the next bit reversed address fragment being generated during a single clock cycle.
A method for interleaving a block of data having a size N, where N is not an integer power of two, comprising:
- generating a current bit reversed address fragment, a next bit reversed address fragment, and a pseudo random address fragment, at least the current bit reversed address fragment and the next bit reversed address fragment being generated during a single clock cycle;
- selecting the current bit reversed address fragment when an address made of the current bit reversed address fragment and the pseudo random address fragment is not greater than N;
- and
- selecting the next bit reversed address fragment when the address is greater than N.
Dependencies are inferred from the claim text.