Multiplierless interpolator for a delta-sigma digital to analog converter

Abstract

A simplified algorithm for digital signal interpolation and a novel architecture to implement the algorithm in an integrated circuit (“IC”) with significant space constraints are presented. According to embodiments of the present invention, the interpolator is divided into two parts. The first part of the interpolator increases the sample rate by a factor of two and smoothes the signal using a half-band Infinite Impulse Response (“IIR”) filter. The second part of the interpolator increases the sample rate of the signal by a factor of thirty-two using a zero-order-hold (“ZOH”) circuit. In one embodiment, the half-band IIR filter is implemented using an all-pass lattice structure to minimize quantization effects. The lattice coefficients are chosen such that the structure can achieve all filter design requirements, yet is capable of being implemented with a small number of shifters and adders, and no multipliers.

Dependencies are inferred from the claim text.