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US 6,313,695 B1Granted
Semiconductor circuit device having hierarchical power supply structure
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTsukasa Ooishi, Hideto Hidaka
Life of this patent
Estimating the term…
Abstract
Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.
Claims33
A semiconductor circuit device having an active state and a standby state, comprising:
- a first main power supply line receiving a first power supply voltage;
- a first sub power supply line;
- a first switching element connected between said first main power supply line and said first sub power supply line, turned on in said active state and turned off in said standby state;
- a second main power supply line receiving a second power supply voltage;
- a first logic circuit connected between said second main power supply line and said first sub power supply line and outputting a first logical level corresponding to said second power supply voltage in said standby state;
- and
- a first constant current circuit disposed to supply a constant current to said first sub power supply line.
4 more elements
A semiconductor circuit device having an active state and a standby state, comprising:
- a main power supply line receiving a power supply voltage;
- a sub power supply line;
- a first switching element connected between said main power supply line and said sub power supply line, turned on in said active state and turned off in said standby state;
- a main ground line receiving a ground voltage;
- a sub ground line;
- a second switching element connected between said main ground line and said sub ground line, turned on in said active state and turned off in said standby state;
- a first logic circuit connected between said main power supply line and said sub ground line and outputting a logical high level in said standby state;
- a second logic circuit connected between said sub power supply line and said main ground line and outputting a logical low level in said standby state;
- a first constant current circuit disposed to supply a constant current to said sub power supply line;
- and
- a second constant current circuit disposed to supply a constant current to said sub ground line.
8 more elements
A semiconductor circuit device having an active state and a standby state, comprising:
- a main power supply line receiving a power supply voltage;
- a sub power supply line;
- a switching P-channel MOS transistor connected between said main power supply line and said sub power supply line, turned on in said active state and turned off in said standby state;
- a main ground line receiving a ground voltage;
- a sub ground line;
- a switching N-channel MOS transistor connected between said main ground line and said sub ground line, turned on in said active state and turned off in said standby state;
- a first logic circuit connected between said main power supply line and said sub ground line and outputting a logical high level in said standby state;
- a second logic circuit connected between said sub power supply line and said main ground line and outputting a logical low level in said standby state;
- a first back gate voltage supply circuit disposed to supply said power supply voltage to a back gate of said switching P-channel MOS transistor in said active state and supply a voltage higher than said power supply voltage to said back gate of said switching P-channel MOS transistor in said standby state;
- and
- a second back gate voltage supply circuit disposed to supply said ground voltage to a back gate of said switching N-channel MOS transistor in said active state and supply a voltage lower than said ground voltage to said back gate of said switching N-channel MOS transistor in said standby state.
8 more elements
A semiconductor device comprising:
- a first main power supply line receiving a first power supply voltage;
- a first sub power supply line;
- a first switch connected between said first main power supply line and said first sub power supply line, and turned off in a standby state;
- a second main power supply line receiving a second power supply voltage;
- a first logic circuit connected between said second main power supply line and said first sub power supply line;
- and
- a first current supply circuit for supplying said first sub power supply line with a current according to amount of a first leak current flowing from/to said first sub power supply line in the standby state.
4 more elements
A semiconductor device comprising:
- a main power supply line receiving a power supply voltage;
- a sub power supply line;
- a first switch connected between said main power supply line and said sub power supply line, and turned off in a standby state;
- a main ground line receiving a ground voltage;
- a sub ground line;
- a second switch connected between said main ground line and said sub ground line, and turned off in the standby state;
- an internal circuit connected to said main power supply line, said sub power supply line, said main ground line and said sub ground line;
- and
- a short circuit for shorting said sub power supply line and said sub ground line in the standby state.
6 more elements
A semiconductor device comprising:
- a first main power supply line receiving a first power supply voltage;
- a first sub power supply line;
- a first transistor connected between said first main power supply line and said first sub power supply line, and turned off in a standby state;
- a second main power supply line receiving a second power supply voltage;
- a first logic circuit connected between said second main power supply line and said first sub power supply line;
- and
- a first back gate voltage supply circuit for supplying a first back gate voltage to a back gate of said first transistor, a first bias voltage between the back gate and a source of said first transistor being smaller in absolute value than the first bias voltage in the standby state when said first transistor turns on.
4 more elements
Dependencies are inferred from the claim text.