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US 6,312,995 B1Granted
MOS transistor with assisted-gates and ultra-shallow “Psuedo” source and drain extensions for ultra-large-scale integration
AssigneeAdvanced Micro Devices, Inc.
InventorBin Yu
Life of this patent
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Abstract
A MOS transistor and a method of fabricating the same for Ultra Large Scale Integration applications includes a composite gate structure. The composite gate structure is comprised of a main gate electrode and two assisted-gate electrodes disposed adjacent to and on opposite sides of the main gate electrode via an oxide layer. Areas underneath the two assisted-gate electrodes form ultra-shallow “pseudo” source/drain extensions. As a result, these extensions have a more shallow depth so as to enhance immunity to short channel effects.
Claims10
A method for fabricating a MOS transistor with assisted-gate electrodes for ULSI, said method comprising the steps of:
- forming a thin gate dielectric layer on a top surface of a semiconductor substrate;
- forming a first doped polysilicon or polysilicon-germanium layer on a surface of said gate dielectric layer;
- patterning said first doped polysilicon or polysilicon-germanium layer and said gate dielectric layer to form a main gate electrode;
- forming a thin cap layer on a top surface of said main gate electrode;
- forming an oxide layer on opposite sides of said main-gate electrode;
- forming first sidewall spacers on each side of said oxide layer;
- forming highly-doped source/drain regions in said semiconductor substrate on opposite sides of said main gate electrode;
- removing said first sidewall spacers;
- annealing said semiconductor substrate so as to activate dopants in said highly-doped source/drain regions;
- forming second doped polysilicon-germanium or polysilicon layer over said main gate electrode and exposed surfaces of said gate dielectric layer;
- patterning said second doped polysilicon-germanium or polysilicon layer and said gate dielectric layer to form a pair of assisted-gate electrodes on opposite sides of said oxide layer and overlying portions of said gate dielectric layer which are located over corresponding areas of the top surface of the semiconductor substrate defining ultra-shallow “pseudo” source/drain regions;
- forming second sidewall spacers adjacent said pair of assisted-gate electrodes;
- removing uncovered portions of said gate dielectric layer on said top surface of said semiconductor substrate to expose said highly-doped source/drain regions and said thin cap layer on the top surface of said main gate electrode;
- and
- forming silicide contacts over said exposed highly-doped source/drain regions and exposed surfaces of said main and assisted-gate electrodes.
12 more elements
A method for fabricating an N-channel MOS transistor with assisted-gate electrodes for ULSI, said method comprising the steps of:
- forming a thin gate dielectric layer on a top surface of a p-type semiconductor substrate;
- forming a doped poly-Si layer on a surface of said gate dielectric layer;
- patterning said doped poly-Si layer and said gate dielectric layer to form a main gate electrode;
- forming a thin cap layer on a top surface of said main gate electrode;
- forming an oxide layer on opposite sides of said main gate electrode;
- forming first sidewall spacers on each side of said oxide layer;
- forming n+ highly-doped source/drain regions in said semiconductor substrate on opposite sides of said main gate electrode;
- removing said first sidewall spacers;
- annealing said semiconductor substrate so as to activate dopants in said n+ highly-doped source/drain regions;
- forming doped poly-Si1−xGex layer over said main gate electrode and exposed surfaces of said gate dielectric layer;
- patterning said doped poly-Si1−xGex layer and said gate dielectric layer to form a pair of assisted-gate electrodes on opposite sides of said oxide layer and overlying portions of said gate dielectric layer which are located over corresponding areas of the top surface of the semiconductor substrate defining ultra-shallow “pseudo” source/drain regions;
- forming second sidewall spacers adjacent said pair of assisted-gate electrodes;
- removing uncovered portions of said gate dielectric layer on said top surface of said semiconductor substrate to expose said n+ highly-doped source/drain regions and said thin cap layer on the top surface of said main gate electrode;
- and
- forming silicide contacts over said exposed n+ highly-doped source/drain regions and exposed surfaces of said main and assisted-gate electrodes.
12 more elements
Dependencies are inferred from the claim text.