Design for test area optimization algorithm

A method of reducing area used during test insertion when using an automatic test pattern generator (ATPG) algorithm, comprising:

• identifying a netlist of an integrated circuit which includes nets;
• identifying a plurality of logical registers of the integrated circuit that are stitched as a shift register;
• transforming the identified logical registers into scan equivalent logical registers, wherein each scan equivalent logical register has an SI port and a D port;
• stitching the scan equivalent logical registers following the order in which the scan equivalent logical registers were extracted;
• and
• identifying the stitched scan equivalent logical registers having the same net on the respective SI ports and D ports;
• and
• replacing the stitched scan equivalent logical registers having the same net on the respective SI ports and D ports with a logical register.

In an electronic design automation system having a processor, memory and an automatic test pattern generation (ATPG) algorithm for designing and testing an integrated circuit, the logic design of the integrated circuit including nets of the integrated circuit providing a netlist, a method of reducing area used during test insertion when using the ATPG algorithm, comprising:

• providing a netlist associated with an integrated circuit;
• screening the netlist to identify flip-flop elements that are stitched as a shift register;
• transforming all the identified flip-flop elements that are stitched as a shift register into respective scan equivalent flip-flop elements with the ATPG algorithm wherein each scan equivalent flip-flop element includes an SI port and a D port;
• stitching the scan equivalent flip-flop elements following the order in which the scan equivalent flip-flop elements were extracted;
• and
• replacing at least one of a plurality of the scan equivalent flip-flop elements having the same net on the SI port and the D port by a flip-flop element.

In an electronic design automation system having a processor, memory and an automatic test pattern generation (ATPG) algorithm for designing and testing an integrated circuit, the logic design of the integrated circuit including nets of the integrated circuit providing a netlist, a method of reducing area used during test insertion when using the ATPG algorithm, comprising:

• providing a list of flip-flop elements that are stitched as a shift register;
• transforming all the identified flip-flop elements that are stitched as a shift register into respective scan equivalent flip-flop elements with the ATPG algorithm wherein each scan equivalent flip-flop element includes an SI port and a D port;
• stitching the scan equivalent flip-flop elements following the order in which the scan equivalent flip-flop elements were extracted;
• and
• replacing at least one of a plurality of the scan equivalent flip-flop elements having the same net on the SI port and the D port by a flip-flop element.