Pre-synthesis test point insertion

A computer readable memory having computer-readable program code embodied therein for causing a computer system to perform a method of inserting test points within an integrated circuit design, said method comprising the steps of:

• a) receiving an unmapped netlist description of said integrated circuit design, said unmapped netlist including a plurality of unmapped logic cells intercoupled by a plurality of nets;
• b) receiving data from an external source, said data indicating a test point to be inserted at a particular net of said unmapped netlist, said data further indicating a specific function to be performed by said test point;
• c) based on said data, inserting a generic test point circuit at said particular net of said unmapped netlist to generate a modified unmapped netlist;
• and
• d) performing a logic synthesis process on said modified unmapped netlist to generate a mapped netlist, wherein said logic synthesis process degenerates said generic test point circuit into an actual test point circuit for performing said specific function.

An electronic design automation system comprising:

• a processor;
• a bus coupled to said processor;
• and
• a computer readable memory coupled to said bus and having stored therein computer readable program code for causing said electronic design automation system to perform a method of test point insertion, said method comprising the steps of:
• a) receiving an unmapped netlist description of said integrated circuit design, said unmapped netlist including a plurality of unmapped logic cells intercoupled by a plurality of nets;
• b) receiving data from an external source, said data indicating a test point to be inserted at a particular net of said unmapped netlist, said data further indicating a specific function to be performed by said test point;
• c) based on said data, inserting a generic test point circuit at said particular net of said unmapped netlist to generate a modified unmapped netlist;
• and
• d) performing a logic synthesis process on said modified unmapped netlist to generate a mapped netlist, wherein said logic synthesis process degenerates said generic test point circuit into an actual test point circuit for performing said specific function.