Method and apparatus for wiring integrated circuits with multiple power buses based on performance

An apparatus for designing a circuit, comprising:

• means for identifying paths in the circuit not satisfying a preselected performance criteria, wherein identified paths are initially designed to be coupled to a first power supply;
• and
• means for redesigning the circuit such that the identified paths are coupled to a second power supply having a higher voltage than the first power supply,
• wherein the higher voltage increases performance of the identified paths such that the identified paths satisfy the performance criteria.

A method of optimizing performance and minimizing power dissipation of a plurality of integrated circuits, comprising:

• simulating the integrated circuits by wiring said integrated circuits with a first voltage power supply;
• identifying paths between said integrated circuits not meeting a delay margin criteria;
• wiring integrated circuits having paths not meeting said delay margin criteria with a second voltage power supply;
• determining and increasing a magnitude of load threshold voltages of all second voltage circuits having input signals emanating from first voltage bus circuits;
• and
• re-simulating the integrated circuits and determining whether all logic paths meet said delay margin criteria and power criteria.

A system for optimizing performance and minimizing power dissipation of a plurality of integrated circuits, comprising:

• means for simulating the integrated circuits by wiring said integrated circuits with a first voltage power supply;
• means for identifying paths between said integrated circuits not meeting a delay margin criteria;
• means for wiring integrated circuits having paths not meeting said delay margin criteria with a second voltage power supply;
• means for determining and increasing a magnitude of load threshold voltages of all second voltage circuits having input signals emanating from first voltage bus circuits;
• and
• means for re-simulating the integrated circuits and determining whether all logic paths meet said delay margin criteria and power criteria.

A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine, to perform method steps for designing a circuit, said method steps comprising:

• identifying paths in the circuit not satisfying preselected performance criteria, wherein the identified paths are initially designed to be coupled to a first power supply;
• and
• redesigning the circuit such that identified paths are coupled to a second power supply having a higher voltage than the first power supply,
• wherein the higher voltage increases performance of the identified paths such that the identified paths satisfy the performance criteria.