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US 6,311,309 B1Granted
Methods and apparatus for simulating a portion of a circuit design
AssigneeAltera Corporation
InventorTimothy J. Southgate
Life of this patent
Estimating the term…
Abstract
A method for simulating a portion of a circuit design is described. The circuit design includes a plurality of design files each corresponding to one of a plurality of design entities in the circuit design. A subset of the design entities is selected. The subset of the design entities corresponds to the portion of the circuit design to be simulated. In response to selection of the subset of the design entities, a netlist is generated under software control directly from the design files associated with the subset of the design entities. The portion of the circuit design is then simulated using the netlist.
Claims34
A method for simulating a portion of a circuit design, the method comprising:
- generating a plurality of design files each corresponding to one of a plurality of design entities in circuit design wherein the plurality of design entities includes fully specified design entities which are sufficiently specified to enable generations of netlists for simulation and partially specified design entities which require further specification for generation of netlists for simulation;
- selecting a subset of the design entities from among the fully specified and partially specified design entities in the circuit design, the subset of the design entities corresponding to the portion of the circuit design and including at least one of the partially specified design entities;
- in response to selecting the subset of the design entities, generating a netlist under software control directly from selected ones of the design files associated with the subset of the design entities, any design file associated with the at least one partially specified design entities being affirmatively excluded from generation of the netlist;
- and
- simulating the portion of the circuit design using the generated netlist.
2 more elements
At least one computer readable medium containing program instructions for simulating a portion of a circuit design, said at least one computer readable medium comprising:
- computer readable code for generating a plurality of design files each corresponding to one of a plurality of design entities in the circuit design wherein the plurality of design entities includes fully specified design entities which are sufficiently specified to enable generation of netlists for simulation and partially specified design entities which require further specification for generation of netlists for simulation;
- computer readable code for selecting a subset of the design entities from among the fully specified and partially specified design entities in the circuit design, the subset of the design entities corresponding to the portion of the circuit design and including at least one of the partially specified design entities;
- computer readable code for, in response to selecting the subset of the design entities, generating a netlist under software control directly from selected ones of the design files associated with the subset of the design entities any design file associated with the at least one partially specified design entities being affirmatively excluded from generation of the netlist;
- and computer readable code for simulating the portion of the circuit design using the generated netlist.
1 more element
A circuit corresponding to a circuit design, the circuit being designed using a simulation method comprising:
- generating a circuit design having a plurality of design files associated therewith, each of the design files corresponding to one of a plurality of design entities in the circuit design wherein the plurality of design entities includes fully specified design entities which are sufficiently specified to enable generation of netlists for simulation and partially specified design entities which require further specification for generation of netlists for simulation;
- selecting a subset of the design entities from among the fully specified and partially specified design entities in the circuit design, the subset of the design entities corresponding to a portion of the circuit design and including at least one of the partially specified design entities;
- in response to selecting the subset of the design entities, generating a netlist under software control directly from selected ones of the design files associated with the subset of the design entities any design file associated with the at least one partially specified design entities being affirmatively excluded from generation of the netlist;
- and simulating the portion of the circuit design using the generated netlist.
1 more element
A computer system comprising:
- a central processing unit;
- a display;
- a keyboard;
- memory having stored therein program instructions for simulating a portion of a circuit design, the memory comprising:
- computer readable code for generating the circuit design comprising a plurality of design files each corresponding to one of a plurality of design entities in the circuit design wherein the plurality of design entities includes fully specified design entities which are sufficiently specified to enable generation of netlists for simulation and partially specified design entities which require further specification for generation of netlists for simulation;
- computer readable code for selecting a subset of the design entities from among the fully specified and partially specified design entities in the circuit design, the subset of design entities corresponding to the portion of the circuit design and including at least one of the partially specified design entities;
- computer readable code for, in response to selecting the subset of the design entities, generating a netlist under software control directly from selected ones of the design files associated with the subset of the design entities any design file associated with the at least one partially specified design entities being affirmatively excluded from generation of the netlist;
- and
- computer readable code for simulating the portion of the circuit design using the generated netlist.
6 more elements
Dependencies are inferred from the claim text.