Method and arrangement for hierarchical control of multiple test access port control modules

A multiple logic unit IC having a limited number of access pins for selecting functions internal to the IC, comprising:

• multiple logic units within the IC, each of the multiple logic units including multiple means for controlling a test-access port (TAP) and including an internal TLM, wherein the TLM includes means for storing having a decodable instruction and a supplemental coded signal;
• and
• means, communicatively coupled with a common interface and with each of the multiple logic units, for controlling the IC via said means for storing, wherein the means for controlling the IC and the multiple means are configured and arranged to use the supplemental coded signal storage circuit for transferring an instruction from one of the multiple logic units.

A multi-core IC having a limited number of access pins for selecting functions internal to the IC, comprising:

• multiple cores within the IC, each of the multiple cores including multiple test-access port (TAP) controllers and including an internal TLM, wherein the TLM includes a storage unit having a TLM register adapted to store a decodable instruction and an extension storage circuit adapted to store a coded bit;
• and
• a chip-level TLM communicatively coupled with a common interface and with each of the multiple cores via the TLM register and the extension storage circuit, wherein the chip-level TLM and the multiple cores are configured and arranged to use the extension storage circuit for indicating when an instruction is to be transferred from a selected one of the multiple cores, wherein the chip level TLM is adapted to load data into the storage unit and, within each of the multiple cores, the chip level TLM responds to the loaded data by coupling and controlling a TMS signal.