Mechanism to simplify built-in self test of a control store unit

A control store for storing control signals which control the operation of a microprocessor, comprising:

• a control store memory comprising a plurality of storage locations, each storage location storing at least one control store word, said control store memory providing an output control store word in response to an input control store address;
• a test enable signal source coupled to the control store memory for activating a control store memory test mode;
• a direct address provider for providing a direct address, wherein said direct address is generated in response to an input address;
• a sequential address provider for providing a next address of the input control store address, said sequential address provider comprising an address incrementor for incrementing said input control store address;
• a jump address provider for providing a jump address, wherein said jump address is generated from the output control store word;
• an address selector coupling to said direct address provider, said sequential address provider, and said jump address provider, said address selector generating the input control store address selected from the direct address, the sequential address, and the jump address,
• wherein when the control store memory is in the control store memory test mode, said address selector selects said input control store address provided to the control store memory from said address incrementor, and wherein when the control store memory is not in the control store memory test mode, said address selector selects the input control store address in response to the output control store word.

A control store for storing control signals in a microprocessor, comprising:

• a control store memory comprising a plurality of storage locations, each storage location storing at least one control store word, and each storage location having a corresponding control store address;
• a test enable signal source coupled to the control store memory for activating a control store memory test mode;
• and
• an address generator coupling to said control store memory for generating a stream of control store access addresses for accessing the control store memory, wherein said control store memory provides a corresponding stream of output control store data retrieved from the storage locations addressed by the control store access addresses, said address generator comprising:
• an address incrementor for producing a first sequence of consecutive control store access addresses when sequential addresses are requested from the control store, and for producing a second sequence of consecutive control store access addresses when the control store memory test mode is activated.

A method of verifying a control store memory, wherein said control store memory comprises a plurality of storage locations, each storage location storing at least one control store word, each of the storage locations corresponds to a valid control store address, wherein all of the valid control store addresses form a valid control store address range, comprising the steps of:

• generating a sequence of sequential control store addresses beginning at a first control store address and incrementing to an ending control store address, wherein said sequential control store addresses generated cover a generated control store address range, said generated control store address range is a superset of said valid control store address range, wherein said ending control store address equals 2N−1, where N is a predetermined positive integer;
• BIST testing at least one control store word corresponding to each of the sequential control store addresses generated when said control store address generated is within said valid control store address range;
• and
• logging out at least one bit of the at least one control store word corresponding to each of the sequential control store addresses generated when said control store address generated is within said valid control store address range.