Explicit state copy in a fault tolerant system using a remote write operation

A method of re-integrating a first processor and at least one second processor in a fault tolerant system, the first and second processors each including registers and at least one memory, comprising the steps of:

• detecting a requirement for re-integration;
• in the first processor, enabling at least one of a copy mode and a remote write operation for a transfer of re-integration information;
• transferring re-integration information from the first processor to the second processor via messages, wherein the step of transferring re-integration information includes the step of accessing, in the first processor, an address mapping of all registers and memory locations in the second processor;
• and
• wherein the transferring step has a plurality of phases, the phases including at least one phase for transferring register information and at least one phase for transferring memory information, and the re-integration information originates from at least one of the registers and memory.

An apparatus for re-integrating a first processor and at least one second processor in a fault tolerant processor system, the first and second processors each having registers and at least one memory, comprising:

• a detector in the first processor that initiates re-integration upon detection that re-integration is required;
• at least one register in the first processor for transferring re-integration information directly to at least one register of the second processor;
• a controller for controlling a state of each processor;
• and
• a dedicated bus for transferring re-integration messages from the first processor to the second processor, wherein each re-integration message includes data and address information and the re-integration messages originate from at least one of the registers and memory.

An apparatus for re-integrating a first processor and at least one second processor in a fault tolerant processor system, the first and second processors each having registers and at least one memory, comprising:

• a detector in the first processor that initiates re-integration upon detection that re-integration is required;
• at least one register in the first processor for transferring re-integration information directly to at least one register of the second processor;
• a controller for controlling a state of each processor;
• a dedicated bus for transferring re-integration messages from the first processor to the second processor, wherein each re-integration message includes data and address information and the re-integration messages originate from at least one of the registers and memory;
• and
• means for performing a remote write operation, wherein the remote write operation enables the first processor to write to any register in the second processor without writing to a corresponding register in the first processor.

An apparatus for re-integrating a first processor and at least one second processor in a fault tolerant processor system, the first and second processors each having registers and at least one memory, comprising:

• a detector in the first processor that initiates re-integration upon detection that re-integration is required;
• at least one register in the first processor for transferring re-integration information directly to at least one register of the second processor;
• a controller for controlling a state of each processor;
• a dedicated bus for transferring re-integration messages from the first processor to the second processor, wherein each re-integration message includes data and address information and the re-integration messages originate from at least one of the registers and memory;
• and
• an interface in each processor that controls a flow of the re-integration messages, wherein the re-integration messages include a type tag that indicates a type of data being transferred.

A method of re-integrating a first processor and at least one second processor in a fault tolerant system, the first and second processors each including registers and at least one memory, comprising the steps of:

• in a first phase, placing the first processor in a copy mode for copying information from a memory of the first processor to a memory of the second processor;
• executing a background program in the first processor that performs a read and a write-back to substantially all locations in the memory in the first processor;
• the first processor, while in the copy mode and upon writing to locations in the memory of the first processor, writing to corresponding locations in the memory of the second processor;
• in a second phase, copying register contents and state information directly from the first processor to the second processor by remote write addressing;
• halting execution by the first and second processors;
• and then
• substantially simultaneously re-starting execution by the first and second processors.

A method of re-integrating a first processor and at least one second processor in a fault tolerant system, the first and second processors each including registers and at least one memory, comprising the steps of:

• in a first phase, placing the first processor in a copy mode for copying information from a memory of the first processor to a memory of the second processor;
• executing a background program in the first processor that performs a read and a write-back to substantially all locations in the memory in the first processor;
• the first processor, while in the copy mode and upon writing to locations in the memory of the first processor, writing to corresponding locations in the memory of the second processor;
• while the first processor is in the copy mode and when information is written to a location in the memory of the first processor, sending to the second processor at least one message of a first type that indicates that the same information is to be written into a corresponding location in the memory of the second processor;
• in a second phase, copying register contents and state information from the first processor to the second processor by remote write addressing;
• in the second phase, sending to the second processor at least one message of a second type indicating a remote write operation by which register contents and state information is written directly to corresponding registers holding state information in the second processor;
• halting execution by the first and second processors;
• and then
• substantially simultaneously re-starting execution by the first and second processors.