Method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency
AssigneeIntel Corporation
InventorsPablo M. Rodriguez, Kenneth R. Douglas, Alper Llkbahar, Harry Muljono
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Abstract
A method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency. A disclosed apparatus includes a signal driver circuit and a strobe signal driver circuit. The signal driver circuit is coupled to generate a cycle for a first signal at a first frequency from a core signal from a core operating at a core clock frequency that is an odd fractional multiple of the first frequency. The strobe signal driver circuit is coupled to generate a strobe signal at an intermediate point of the cycle to allow latching of the first signal triggered by the strobe signal.
Claims29
An apparatus comprising:
- a first signal driver circuit coupled to generate a cycle for a first signal at a first frequency from a core signal from a core operating at a core clock frequency that is an odd fractional multiple of the first frequency;
- and
- a strobe signal driver circuit coupled to generate a strobe signal at an intermediate point of the cycle to allow latching of the first signal triggered by the strobe signal.
An apparatus comprising:
- a processor having a first portion operating at a first frequency and having a source synchronous interface, the source synchronous interface generating a plurality of signals and a clock, the clock transitioning at an intermediate point of a cycle of said plurality of signals, said clock and said plurality of signals transitioning at a second frequency that is an odd fraction of said first frequency;
- and
- a memory circuit coupled to said processor, the memory circuit having a memory interface circuit operating at said second frequency and that latches said plurality of signals using said clock that is generated by said processor.
A method comprising:
- transmitting a data cycle for a data signal at a first frequency, the first frequency being an odd fraction of a core frequency of a core from which the data signal originates;
- and
- transmitting a strobe signal synchronized to transition at an intermediate point of the data cycle.
An apparatus comprising:
- means for providing a first interface signal on a first signal line from a first core signal, the first interface signal transitioning on both rising and falling edges of a core clock signal;
- means for providing a strobe signal that transitions at intermediate points between rising and falling edges of the core clock signal to allow latching of the first interface signal using the strobe signal.
Dependencies are inferred from the claim text.