Apparatus and method for changing processor clock ratio settings
AssigneeEdwin H. Taylor
InventorsEdwin J. Pole, II, John T. Orton, Cau L. Nguyen, Gurbir Singh, Xia Dai, Ravi Nagaraj
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Abstract
A processor has an external pin that can be asserted to lock in new clock ratio information dynamically. A state machine of the processor defines a stop grant state that is utilized to halt the internal clocking signal of the processor. A storage location, such as a register, is utilized to load new clock frequency information into the clock generator circuit of the processor. De-asserting the external pin of the processor causes the processor to resume normal operations, but at the newly set clock frequency.
Claims20
An apparatus for changing a clock frequency generated by a clocking circuit of a processor comprising:
- at least one pin of the processor;
- a state machine that defines a normal operating state of the processor and a change clock state, the processor transitioning from the normal operating state to the change clock state whenever a signal is asserted at the at least one pin, and from the change clock state to the normal operating state upon de-assertion of the signal;
- and
- means for entering new clock frequency information to the clocking circuit when the processor is in the change clock state.
A method of changing a clock frequency of a processor comprising the steps of:
- (a) asserting a first signal while the processor is operating in a normal state, the first signal causing the processor to first enter a change clock state or a stop clock state;
- (b) locking a new clock ratio into a clock generator circuit of the processor while in either the change clock state or the stop clock state;
- (c) de-asserting the first signal causing the processor to transition from the change clock state to the normal state, wherein the clock frequency of the processor in the normal state is set by the new clock ratio.
A method of changing a clock frequency of a processor comprising the steps of:
- (a) asserting a stop clock signal while the processor is operating in a normal state, the stop clock signal causing the processor to enter a stop grant state, an internal clock signal of the processor being halted in the stop grant state;
- (b) halting a clock generator circuit of the processor by de-asserting an external signal coupled to the clock generator circuit, the clock generator circuit producing the internal clock signal of the processor;
- (c) locking new clock ratio information into the clock generator circuit;
- (d) starting the clock generator circuit by asserting the external signal;
- and
- (e) de-asserting the stop clock signal.
A processor comprising:
- a pin;
- a state machine that defines a normal operating state of the processor and a change clock state, the processor transitioning from the normal operating state to the change clock state whenever the pin is asserted, and from the change clock state to the normal operating state upon de-assertion of the pin;
- and
- a storage location that contains new clock frequency information provided to a clocking circuit when the processor is in the change clock state.
Dependencies are inferred from the claim text.