Just-in-time register renaming technique
AssigneeInternational Business Machines Corporation
InventorsDung Quoc Nguyen, Hung Qui Le
Life of this patent
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Abstract
A target register of an instruction is assigned a rename register in response to the instruction being issued. That is, the target register is renamed at issue time, not at dispatch time. To handle a new deadlock issue this gives rise to, rename register allocation/deallocation logic, according to the present invention, includes logic for allocating and deallocating two sets of rename registers, one set from a regular rename buffer and another set from an overflow rename buffer. According to this allocation/deallocation logic, if the oldest dispatched, noncompleted instruction is ready for assignment of a rename register and the regular rename buffer is full, then a rename register is assigned from the overflow rename buffer to this instruction.
Claims11
A method of assigning rename registers to instructions being processed in a processor, comprising the steps of:
- dispatching instructions;
- and
- assigning, to a dispatched instruction having a target register, a rename register from among a plurality of rename registers, wherein the assigning of a rename register includes assigning the rename register in response to availability of source operands for the dispatched instruction.
An apparatus for processing instructions, wherein the processing includes assigning rename registers to certain of the instructions being processed, comprising:
- a) means for dispatching instructions;
- and
- b) means for assigning, to a dispatched instruction having a target register, a rename register from among a plurality of rename registers, wherein the assigning means includes:
- b1) means for assigning the rename register in response to availability of source operands for the dispatched instruction.
An information handling system, comprising:
- a) a memory for storing computer program instructions, the instructions having a program order;
- and
- b) a processor, coupled to the memory, for receiving and processing the instructions, comprising:
- b1) a plurality of architected registers;
- b2) a plurality of rename registers;
- b3) a dispatch unit for dispatching the instructions received from the memory, the instructions specifying operations for the processor, and wherein a number of the instructions identify ones of the architected registers for respective source operands, and ones of the architected registers for respective destination operands;
- and
- b4) rename register allocation/deallocation logic, for allocating and deallocating registers to the dispatched instructions from among the plurality of rename registers, wherein such a rename register stores one of its assigned instruction's destination operands resulting from execution by the processor until the rename register's destination operand is written to its instruction's designated architected register, and wherein the assigning of one of the rename registers by the allocation/deallocation logic to a first one of the dispatched instructions includes assigning in response to a source operand for the first instruction being available in either:
- i) the rename register assigned by the allocation/deallocation logic for a destination operand of a second one of the instructions, or ii) one of the architected registers designated by the second instruction for the destination operand of the second instruction.
Dependencies are inferred from the claim text.