Computer memory controller with self refresh performed during memory back-up operation in case of power failure
AssigneeNEC Corporation
InventorTsuyoshi Kishino
Life of this patent
Estimating the term…
Abstract
A computer memory controller comprises a dynamic random access memory (DRAM) timing control section that provides, during memory back-up operation mode, self-refresh timing to a DRAM array having self-refresh function. The memory controller also comprises a refresh/back-up control section that provides information as to memory back-up state to the DRAM timing control section. A DRAM identification mode register is provided. When a DRAM array without a self-refresh function is mounted, the state of the register changes. The state of the register is fed to the DRAM timing control section, thereby to provide timing according to the conventional column address strobe (CAS) before row address strobe (RAS) or CBR refresh method to the DRAM array.
Claims3
A computer memory controller for a memory in the form of a DRAM having a memory back-up function in case of power failure, the computer memory controller operable to cause the DRAM to perform self refresh operations during the memory back-up operation, the controller comprising:
- a back-up control section comprising:
- a back-up control signal generator outputting a back-up control signal in response to a power failure indicative (PFI) signal;
- a DRAM identification mode register that detects whether a DRAM without a self-refresh function is in use and outputs a DRAM identification signal accordingly, the back-up control section providing a back-up trigger signal according to the logical combination of the back-up control signal and the DRAM identification signal;
- and
- a refresh trigger signal generator that receives the back-up trigger signal and outputs a refresh operation trigger signal accordingly;
- and
- a DRAM timing control section that receives as inputs the refresh operation trigger signal and the back-up trigger signal and, during memory back-up operation mode, outputs a self-refresh timing signal to the DRAM when the DRAM is detected as having a self-refresh function and outputs a refresh timing signal other than a self-refresh timing signal when the DRAM is detected as not having a self-refresh function.
Dependencies are inferred from the claim text.