Architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media

A circuit comprising:

• means for receiving a first series of data packets having a first bit-width and presenting a second series of data packets having a second bit-width in response to said first series of data packets, said receiving means comprising a packer circuit and an encoder/serializer circuit;
• and
• means for presenting a third series of data packets having said first bit-width in response to said second series of data packets, said presenting means comprising a decoder/deserializer circuit and an unpacker circuit.

A method for transmitting data having a first bit-width over media having a second bit-width comprising the steps of:

• (a) receiving a first series of data packets having said first bit-width, generating a second series of data packets having said second bit-width in response to said first series of data packets, and packing, encoding/serializing, and presenting said second series of data packets to said media;
• and
• (b) receiving, decoding/deserializing, and unpacking said second series of data packets, and generating a third series of data packets having said first bit-width in response to said second series of data packets.