Direct memory access controller with split channel transfer capability and FIFO buffering

A data processing device, comprising:

• a central processing unit (CPU) operable to execute software instructions stored in a program memory circuit connected to the central processing unit;
• a data memory circuit operable to store data to be processed by the processing device;
• and
• a direct memory access (DMA) controller having a plurality of DMA channels,
• wherein each DMA channel has associated programmable read address circuitry and programmable write address circuitry, each DMA channel operable to transfer data from or to the data memory circuit, the DMA controller comprising:
• a FIFO buffer connected to a data bus to receive a plurality of data elements received in response to the read address circuitry associated with a selected one of the plurality of DMA channels, the FIFO buffer operable to hold a portion of the plurality of data elements until the portion of the plurality of data elements is written in response to the write address circuitry of the selected one of the plurality of DMA channels;
• and
• wherein the FIFO buffer is operable to be selectively associated with any one of the plurality of DMA channels, such that non-selected ones of the plurality of DMA channels are operable to transfer data from or to the data memory without use of the FIFO.