Systems and methods for on-chip storage of virtual connection descriptors

A method of locating virtual connection descriptors (VCDs) in a networking device, the device including a processor coupled to a first memory for storing a first plurality of VCDs, and the processor including a processing engine, a second memory for storing a second plurality of VCDs, and a content-addressable memory (CAM) that stores addresses of the second plurality of VCDs stored in the second memory, the method comprising:

• sending a first identifier from the processing engine to the CAM, wherein the first identifier is associated with a first VCD;
• determining in the CAM whether the first VCD is stored in the second memory;
• and
• responding to the processing engine with one of a hit signal if the first VCD is stored in the second memory and a miss signal if the first VCD is not stored in the second memory.

A single-chip network device, wherein the device is coupled to a local memory for storing a first plurality of virtual connection descriptors (VCDs), the device comprising:

• a) a cache memory for storing a second plurality of VCDs;
• b) a processing engine, coupled to the local memory and to the cache memory, for processing VCDs;
• and
• c) a content-addressable memory (CAM), coupled to the processing engine, wherein the CAM stores cache addresses of the second plurality of VCDs stored in the cache memory;
• wherein the processing engine sends a first VCD identifier associated with a first VCD to the CAM, wherein the CAM reads the first VCD identifier and responds to the processing engine with one of a hit signal indicating that the first VCD is stored in the cache memory and a miss signal indicating that the first VCD is not stored in the cache memory.

A networking system device comprising:

• a local memory to store a first plurality of virtual connection descriptors (VCDs);
• and
• a network processor, including:
• a) a cache memory to store a second plurality of VCDs;
• b) a processing engine, coupled to the local memory and to the cache memory, to process VCDs;
• and
• c) a content-addressable memory (CAM), coupled to the processing engine, to store cache addresses of the second plurality of VCDs stored in the cache memory, each cache address being cross-referenced to a VCD identifier associated with one of the second plurality of VCDs;
• the device having the processing engine send a first VCD identifier associated with a first VCD to the CAM that reads the first VCD identifier and responds to the processing engine with one of:
• a hit signal indicating that the first VCD identifier has a corresponding cache address in the CAM, the processing engine then accessing the first VCD in the cache memory using the corresponding cache address;
• and
• a miss signal indicating that the first VCD identifier does not have a corresponding cache address in the CAM, the processing engine then accessing the first VCD in the local memory.

An apparatus comprising:

• a cache to store a first set of virtual connection descriptors (VCDs);
• a content-addressable memory (CAM) to store cache memory addresses, each cache memory address linked to a VCD identifier that corresponds to a given one of the first set of VCDs, the CAM having the capability to determine if a VCD resides in the cache when the CAM receives a VCD identifier by:
• searching for the received VCD identifier to determine if a corresponding cache address exists in the CAM for the received VCD identifier;
• and
• returning one of a hit signal if a corresponding cache address exists for the received VCD identifier, the hit signal including the corresponding cache address, and a miss signal if the corresponding cache address does not exist for the received VCD identifier;
• a processing engine coupled to the cache and the CAM to process VCDs by:
• receiving a VCD identifier associated with a given VCD;
• sending the VCD identifier to the CAM for the CAM to determine if the associated VCD exists in the cache;
• and
• performing one of the following in response to the CAM returning one of a hit signal and a miss signal by:
• accessing the given VCD from the cache if the CAM returns a hit signal;
• and
• accessing the given VCD from a different memory if the CAM returns a miss signal.

A system comprising:

• a first memory having a first set of virtual connection descriptors (VCDs);
• a network processor having:
• a second memory to store a second set of VCDs;
• a content-addressable memory (CAM) to store memory addresses of the second memory, each memory address linked to a VCD identifier that corresponds to one of the second set of VCDs, the CAM having the capability to determine if a VCD resides in the second memory when the CAM receives a VCD identifier by:
• searching for the received VCD identifier to determine if a corresponding memory address exists in the CAM for the received VCD identifier;
• and
• returning one of a hit signal if a corresponding memory address exists for the received VCD identifier and a miss signal if a corresponding memory address does not exist for the received VCD identifier;
• a processing engine coupled to the first memory, second memory, and CAM, to process VCDs by:
• receiving a VCD identifier associated with a given VCD;
• sending the VCD identifier to the CAM for the CAM to determine if the associated VCD exists in the second memory;
• and
• performing one of the following in response to the CAM returning one of a hit signal and a miss signal by:
• accessing the given VCD from the second memory if the CAM returns a hit signal;
• and
• accessing the given VCD from the first memory if the CAM returns a miss signal.

A method comprising:

• receiving a virtual connection descriptor (VCD) identifier associated with a given VCD;
• sending the VCD identifier to a content-addressable memory (CAM) for the CAM to determine if the associated VCD exists in an on-chip memory, the CAM making this determination by searching for the VCD identifier in the CAM to determine if a corresponding on-chip memory address exists for the VCD identifier, and the CAM to return one of a hit signal if a corresponding on-chip memory address exists and a miss signal if a corresponding on-chip memory address does not exist;
• and
• performing one of the following in response to the CAM returning one of a hit signal and a miss signal by:
• accessing the given VCD from the on-chip memory if the CAM returns a hit signal;
• and
• accessing the given VCD from an off-chip memory if the CAM returns a miss signal.