Hardware efficient fast hadamard transform engine

A Fast Hadamard Transform apparatus having a plurality of transform stages, employed by a wireless telecommunication system for detecting and correcting errors that occur during the transmission of coded signal blocks having N bits, each stage of said apparatus comprising:

• an adder having an output terminal and a subtractor having an output terminal, said adder and said subtractor configured to receive N/2 signal pairs within each received signal block, so as to generate intermediate coefficients;
• a first memory unit coupled to the output terminal of said adder and the output terminal of said subtractor, said memory unit configured to receive a first specifiable sequence of said intermediate coefficients from said adder and a second specifiable sequence of said intermediate coefficients from said subtractor;
• a second memory unit coupled to the output terminal of said subtractor so as to receive a third specifiable sequence of said intermediate coefficients from said subtractor, such that said first memory unit and said adder provide concurrently a plurality of intermediate coefficient signal pairs to a subsequent transform stage, and said first and second memory units provide concurrently a plurality of other intermediate coefficient signal pairs to said subsequent transform stage.