Efficient low pass filter stage for a decimation filter
AssigneeCirrus Logic, Inc.
InventorKeith S. Albright
Life of this patent
Estimating the term…
Abstract
A decimation filter has a low pass first stage of filtering in which multiple taps from a plurality of delay stages are summed together and then integrated to thereby provide suppression of high frequency noise in the input signal.
Claims25
A method for digitally filtering a bit stream signal of one bit wide comprising the steps of:
- a) delaying said bitstream signal in a plurality of serially connected delay stages;
- b) summing together the true or complement of a selected group of said delay stages to form a summed signal, said group being greater than two;
- and,
- c) integrating said summed signal in a plurality of integration stages to form a filtered output signal.
A method for digitally filtering a bit stream signal of one bit wide comprising the steps of:
- a) delaying said bit stream signal in a plurality of serially connected delay stages;
- b) addressing a ROM with a selected group of said delay stages, said group being greater than two;
- and,
- c) integrating an output of said ROM in a plurality of integration stages to form a filtered output signal.
Apparatus comprising a series connection of delay stages having an input terminal for receiving an input signal and an output terminal, wherein a select group of the true and complementary signals derived from the nodes of said series connection of delay stages are combined together in a combination circuit to provide a summed signal, said summed signal coupled to an input terminal of an integration stage comprising a plurality of integrators wherein an output terminal of said plurality of integrators provides an output signal which is a filtered version of said input signal.
Apparatus comprising a series connection of delay stages having an input terminal for receiving an input signal and an output terminal, wherein a select group of the true and complementary signals derived from the nodes of said series connection of delay stages are summed together to provide a summed signal, said summed signal coupled to an input terminal of an integrator stage comprising a plurality of integrators wherein an output terminal of said plurality of integrators provides an output signal such that said output signal divided by said input signal is characterized by a filter response having zeros at frequencies which are not all related to each other by a factor of X/Y where X and Y are integers, and wherein said output signal is coupled to the input of a decimation stage which has a decimated output signal.
A low pass discrete time filter comprising:
- a) a plurality of serially connected delay stages having an input terminal for receiving an input signal;
- b) a means for detecting the state of signals at selected nodes of said serially connected delay stages and for generating a sum signal which corresponds to the sum of one of the true or complement signals present at said selected nodes;
- c) a series combination of two or more integrator stages which receives said sum signal and which provides an output signal which is proportional to said input signal after it has been low pass filtered;
- and,
- d) a decimation stage which has an input terminal coupled to said output signal and an output terminal.
In a discrete time low pass filtering process which includes the steps of integrating, summing, delaying, and decimating a data bit stream, wherein said summing step comprises summing one of the true or complement signals at a selected plurality of nodes of a delay circuit used to perform the delaying step, the improvement comprising integrating more than once in a plurality of serially connected integrators.
Dependencies are inferred from the claim text.