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US 6,310,928 B1Granted
PLL circuit
AssigneeKabushiki Kaisha Toshiba
InventorTakao Yunome
Life of this patent
Estimating the term…
Abstract
A PLL circuit comprises a storage/control circuit for storing, in an associated manner, a plurality of PLL output frequencies to be designated, lock ranges including the PLL output frequencies in their central regions respectively, and information on the number of stages of delay circuits. The number of stages of the delay circuits having a lock range including a designated PLL output frequency in its central region is selected and controlled by the storage/control circuit. A frequency divider selects and controls a frequency division ratio for obtaining a PLL output frequency on the basis of a frequency of a reference signal.
Claims15
A PLL circuit comprising:
- a ring oscillator used as a voltage controlled oscillator;
- a frequency divider for dividing a frequency of an output signal of the ring oscillator;
- a phase comparator for comprising a frequency-division output from the frequency divider and a reference signal;
- a control voltage generating circuit for generating a control signal for controlling the number of stages of delay circuits of the ring oscillator on the basis of a designated PLL output frequency;
- and
- a data table for storing information on the number of stages of the delay circuits of the ring oscillator having a lock range including the designated PLL output frequency in a central region thereof;
- wherein the control circuit controls reading-out the information from the data table with reference to the designated PLL output frequency, and generates a control signal for controlling the number of the stages of the delay circuits of the ring oscillator and a frequency division ratio of the frequency divider on the basis of read-out information.
4 more elements
A PLL circuit comprising:
- a ring oscillator used as a voltage controlled oscillator;
- a frequency divider for dividing a frequency of an output signal of the ring oscillator;
- a phase comparator for comprising a frequency-division output from the frequency divider and a reference signal;
- a control voltage generating circuit for generating a control signal for controlling the number of stages of delay circuits of the ring oscillator on the basis of a designated PLL output frequency;
- and
- a data table for storing information on the number of the stages of the delay circuits of the ring oscillator having a proper lock range in accordance with a relationship between the designated PLL output frequency and a frequency of the reference signal to be inputted to the phase comparator;
- wherein the control circuit controls reading-out the information from the data table with reference to the designated PLL output frequency and the frequency of the reference signal, and generates a control signal for controlling the number of the stages of the delay circuits of the ring oscillator and the frequency division ration of the frequency divider on the basis of the read-out information.
4 more elements
A PLL circuit comprising:
- a ring oscillator used as a voltage controlled oscillator;
- a frequency divider for dividing a frequency of an output signal of the ring oscillator;
- a phase comparator for comparing a frequency-division output from the frequency divider and a reference signal;
- a control voltage generating circuit for generating a control voltage to be inputted to the ring oscillator in accordance with a comparison output from the phase comparator;
- and
- a control circuit for generating a control signal for controlling the number of stages of delay circuits of the ring oscillator on the basis of a designated PLL output frequency, wherein the frequency divider comprises:
- a plurality of flip-flop circuits connected in multiple stages;
- and
- a multiplexer for selecting a stage for outputting a frequency-division output in the flip-flop circuits connected in multiple stages, and supplying an output from the selected stage to the phase comparator.
6 more elements
A PLL circuit comprising:
- a ring oscillator used as a voltage controlled oscillator;
- a frequency divider for dividing a frequency of an output signal of the ring oscillator;
- a phase comparator for comparing a frequency-division output from the frequency divider and a reference signal;
- a control voltage generating circuit for generating a control voltage to be inputted to the ring oscillator in accordance with a comparison output from the phase comparator;
- and
- a control circuit for generating a control signal for controlling the number of stages of delay circuits of the ring oscillator on the basis of a designated PLL output frequency,
- wherein the ring oscillator is formed by selectively connecting one of a plurality of said delay circuits having stage numbers different from each other, and the plurality of delay circuits provide lock ranges overlapping each other.
4 more elements
Dependencies are inferred from the claim text.