Method and apparatus for generating variable rate synchronization signals
AssigneeThomson Consumer Electronics, Inc.
InventorsBarth Alan Canfield, Harold Blatter
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Abstract
A programmable synchronizing system for selectively providing synchronizing signals at different rates, such as for incorporation in a video signal decompression system, includes an oscillator and a programmable counter. The programmable counter is conditioned to count pulses from the oscillator by alternate moduli in predetermined sequences to generate the synchronizing signals. The desired synchronization rate is effectively the average of the counter output resulting from counting by the alternate moduli.
Claims15
Synchronizing signal generating circuitry, for selectably providing synchronizing signals having different frequencies, comprising:
- a phase locked loop source of a clock signal;
- a divider, coupled to and external to said source, for dividing said clock signal to generate said synchronizing signals;
- a source of reference signal;
- a detector for detecting a difference between the synchronizing signal and said reference signal;
- selection circuitry, responsive to said difference and said synchronizing signal for conditioning said divider to divide the clock signal by a sequence of alternate divisors, wherein said divider divides said clock signal by each said alternate divisor in a sequence for no less than a period of said synchronizing signal.
In an MPEG-compatible compressed video signal processing apparatus, synchronizing signal generating apparatus for selectably generating synchronizing signals at different frequencies, comprising:
- a source of MPEG-compatible compressed video signal;
- an inverse transport processor including means responsive to said MPEG-compatible compressed video signal for generating a system clock signal for energizing at least in part said source and said inverse transport processor;
- an MPEG-compatible video signal decompressor coupled to said inverse transport processor, including means responsive to said MPEG-compatible compressed video signal for providing a control signal determinative of a frame rate decompressed said video signal is to be displayed;
- phase locking circuitry, responsive to said MPEG-compatible compressed video signal for generating a system clock for operating, at least in part, said inverse transport processor;
- a phase locked loop, coupled to said system clock for generating a pixel clock signal having a frequency higher than said system clock, for operating, at least in part, said MPEG-compatible video signal decompressor;
- a frequency divider, for dividing the frequency of said pixel clock to generate said synchronizing signals;
- and
- sequencing circuitry, responsive to said control signal and to generated said synchronizing signals for selecting from a plurality, greater than two, of alternative divisors, for applying selected divisors to said frequency divider, said sequencing circuitry selecting different sequences of divisors for different frequency synchronizing signals indicated by said control signal.
Synchronizing signal generating circuitry, for selectably providing synchronizing signals having different frequencies, comprising:
- a source of a clock signal having a frequency;
- a divider coupled to said source for dividing said clock signal frequency to generate said synchronizing signals;
- and
- sequencing circuitry, responsive to said synchronizing signals, for applying a plurality of different sequences of alternate divisors to said divider to produce different output synchronizing signal frequencies, at least some divisors being applied in repeating sequences of alternate divisors with respective divisors in a sequence being applied to said divider for at least one period of said synchronizing signal.
Synchronizing signal generating circuitry, for selectably providing vertical synchronizing signals having different frequencies, comprising:
- a source of synchronizing reference signal;
- a source of a clock signal frequency;
- a divider coupled to said source for dividing said clock signal frequency to generate said synchronizing signals;
- a detector, responsive to said synchronizing reference signal and said synchronizing signal for determining phase/frequency differences there between;
- sequencing circuitry, responsive to said synchronizing signals and said differences, for applying a plurality of alternate divisors to said divider, to produce said synchronizing signal, said sequencing circuitry having facility to cause said divider to produce different synchronizing signal output frequencies by applying different sequences of alternate divisors to said divider, and wherein respective divisors are applied to said divider for no less than one period of said synchronizing signal.
Synchronizing signal generating circuitry, for selectably providing synchronizing signals having different frequencies, comprising
- a source of a clock signal;
- a divider coupled to said source for dividing said clock signal to generate said synchronizing signals;
- and
- circuitry for conditioning said divider to divide the clock signal by a sequence of alternate divisors;
- wherein
- said source comprises a controlled oscillator, having a control input port and an output port at which a primary clock signal is available;
- and
- a divider circuit coupled to said output port, for dividing said primary clock signal by a constant factor to provide said clock signal;
- wherein
- said controlled oscillator provides a primary clock signal of 81 Mhz, said divider circuit divides the primary clock signal by 1200, and said circuitry for conditioning said divider to divide the clock signal conditions the divider to alternately divide by 1000 and 1001.
A method for generating synchronizing signal comprising:
- providing a clock signal having a frequency which is a non-integer multiple of the synchronizing signal frequency;
- providing a reference signal;
- providing a threshold value;
- frequency dividing the clock signal in a frequency divider having an output at which said synchronizing signal is available;
- generating a signal representative of differences in phase between the synchronizing signal from said divider and the reference signal;
- comparing the threshold value with said signal representative of differences;
- selecting one of a first and second divisor value if the signal representative of differences is greater than the threshold;
- or
- selecting one of a third and fourth divisor value if the threshold is greater than the signal representative of differences;
- and
- causing said frequency divider to divide said clock signal by respective selected divisors.
Dependencies are inferred from the claim text.