System for increasing the definition in converting a digital datum in a PWM signal for driving a full-bridge output stage

A method for driving an inductive load through a power output stage, the method comprising the steps of:

• increasing a definition of conversion of a PWM signal using an up/down N-bit counter by
• increasing a dimension of an N-bit digital value to an N+2 bit digital value, the N+2 bit digital value having two least significant bits and N most significant bits,
• using the two least significative bits to select one among three intermediate levels between two consecutive values representable by an N-bit digital value according to a predefined table of combinations,
• using the N most significative bits to store four values in respective ones of four registers, the four stored values comprising the N-bit digital value, a complement of the N-bit digital value, the N-bit digital value incremented by 1, and a complement of the N-bit input digital value incremented by 1, and
• using the two least significative bits and an up/down output signal of the up/down N-bit counter to select a pair of the four stored values to be compared during each up-counting phase and down-counting phase of the up/down N-bit counter as a function of the predefined table of combinations to produce an increased definition PWM signal;
• and driving the inductive load with the power stage using the increased definition PWM signal.

A system for driving an inductive load comprising:

• a power output stage connected to the inductive load;
• and
• conversion means for converting an N-bit digital value into a PWM signal for the power output stage, said conversion means comprising
• an N-bit comparator connected to said power output stage,
• an up/down N-bit counter connected to said N-bit comparator,
• a register having a capacity of N+2 bits for storing an N+2 bit digital value based upon an N-bit digital value,
• four additional registers for storing four values comprising the N-bit digital value, a complement of the N-bit digital value, the N-bit digital value incremented by 1, and a complement of the N-bit digital value incremented by 1, respectively, and
• a multiplexer for selecting a pair of the four stored values in said four additional registers to be compared in said N-bit comparator when said up/down N-bit counter is counting up and is counting down based upon a combination of values of the two least significative bits of the N+2 bit digital value and by an up/down signal of said up/down N-bit counter.

A circuit for increasing a definition of a conversion of a digital value in a PWM signal using an up/down N-bit counter, the circuit comprising:

• means for increasing a dimension of an N-bit input digital value to N+2 bit digital value, the N+2 bit digital value having N most significant bits and two least significant bits;
• means for using the two least significative bits to select one among three intermediate levels between two consecutive values representable by the N-bit input digital value according to a predefined table of combinations;
• means for using the N most significative bits to store four values comprising the N-bit digital value, a complement of the N-bit digital value, the N-bit digital value incremented by 1, and a complement of the N-bit digital value incremented by 1;
• an up/down counter;
• and
• means for using the two least significative bits and an up/down output signal of the up/down N-bit counter to select a pair of the four stored values to be compared during each up-counting phase and down-counting phase of the up/down N-bit counter as a function of the predefined table of combinations.

A driving circuit for a brushless DC multi-phase motor of a type comprising a plurality of phase windings, said driving circuit comprising:

• a full-bridge power output stage for each phase winding of the motor;
• and
• conversion means for converting an N-bit digital value into a PWM signal for the power output stage, said conversion means comprising
• an N-bit comparator connected to said power output stage,
• an up/down N-bit counter connected to said N-bit comparator,
• a register having a capacity of N+2 bits for storing an N+2 bit digital value based upon an N-bit digital value,
• four additional registers for storing four values comprising the N-bit digital value, a complement of the N-bit digital value, the N-bit digital value incremented by 1, and a complement of the N-bit digital value incremented by 1, respectively, and
• a multiplexer for selecting a pair of the four stored values in said four additional registers to be compared in said N-bit comparator when said up/down N-bit counter is counting up and is counting down based upon a combination of values of the two least significative bits of the N+2 bit digital value and by an up/down signal of said up/down N-bit counter.

A driving circuit for a brushless DC multi-phase motor of a type comprising a plurality of phase windings, said driving circuit comprising:

• a full-bridge power output stage for each phase winding of the motor;
• and
• conversion means for converting an N-bit digital value into a PWM signal for the power output stage, said conversion means comprising
• means for increasing a dimension of an N-bit input digital value to N+2 bit digital value, the N+2 bit digital value having N most significant bits and two least significant bits,
• means for using the two least significative bits to select one among three intermediate levels between two consecutive values representable by the N-bit input digital value according to a predefined table of combinations,
• means for using the N most significative bits to store four values comprising the N-bit digital value, a complement of the N-bit digital value, the N-bit digital value incremented by 1, and a complement of the N-bit digital value incremented by 1,
• an up/down counter, and
• means for using the two least significative bits and an up/down output signal of the up/down N-bit counter to select a pair of the four stored values to be compared during each up-counting phase and down-counting phase of the up/down N-bit counter as a function of the predefined table of combinations.