Content addressable memory cells and systems and devices using the same
AssigneeSilicon Aquarius, Inc.
InventorCraig Waller
Life of this patent
Estimating the term…
Abstract
A content addressable memory cell 920 includes a first storage element 922a for storing information and a first transistor 921a for selectively transferring charge representing information from a first bitline 924a to the first storage element 922a. A second transistor 921b selectively transfers charge representing information from a second bitline 924b to a second storage element 922b. First and second comparelines 925a, 925b carry first and second bits of a comparand to a comparator 905, 906, 908 which compares the first and second bits of the comparand with information stored on the first and second storage elements. In response, comparator 905, 906, 908 selectively controls a voltage on a corresponding one of a plurality of matchline 909.
Claims6
A telecommunications subsystem comprising:
- an input port for receiving a stream of information;
- a plurality of output ports, a selected one of said output ports transmitting said stream of information received by said input port to a next node in a telecommunications network;
- and
- a content addressable memory for storing a translation table, said translation table containing information for selecting said selected one of said output ports, comprising:
- a plurality of conductors;
- a plurality of memory cells each having a first transistor for exchanging charge between a first one of said conductors and a storage element and a second transistor for exchanging charge between said storage element and a second one of said conductors;
- and
- a comparator circuitry for comparing data presented on a selected pair of said plurality of conductors with data stored on said storage elements of a corresponding pair of said memory cells and selectively pulling-down a voltage on an associated matchline.
Dependencies are inferred from the claim text.